Arm Limited

Gary Campbell

David Michael Bull

Paul Kimelman

Ian Field

Peter Guy Middleton

Simon Axford

An interrupt controller and method are provided for handling interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises pend logic for receiving interrupt requests generated by the plurality of interrupt sources, and for each interrupt request, determining whether to accept that interrupt request for handling by the interrupt controller. Interrupt handling logic then selects an interrupt request from amongst those interrupt requests accepted by the pend logic, and generates an indication of the interrupt routine to be executed by a processor to process that interrupt request. The pend logic is arranged, for each of the interrupt sources, to detect a transition of the associated interrupt request from an unset state to a set state, and to accept the interrupt request upon such detection. The pend logic also receives an exit signal indicating completion of the interrupt routine by the processor, and if the associated interrupt request is in the set state on receipt of the exit signal, re-accepts that interrupt request. By such an approach, the interrupt controller can automatically support both level interrupt requests and pulsed interrupt requests without the need for software configuration.

Interrupt controller and method for handling interrupts

The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access. Instead, prediction logic is arranged to predict the one or more predetermined attributes, and clock generation logic is responsive to the predictive predetermined attributes from the prediction logic to select which one of the memory units is to be clocked during performance of the access, and to issue a clock signal to that memory unit. Checking logic is then provided to determine whether the predetermined attributes generated by the attribute generation logic agree with the predicted predetermined attributes, and if not, to reinitiate the access, in which event the clock generation logic is arranged to reselect one of the memory units using the predetermined attributes as determined by the attribute generation logic. This approach enables high speed processing of access requests, whilst achieving significant power savings over prior art systems where multiple memory units are clocked speculatively in parallel.

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Corby, United Kingdom

Gary Campbell