Synopsys, Inc.

Other

Avant! Corporation

Avant&excl; Corporation

Gary Bruce Lipton

Jonathan Calvin White

Harry Clarkson Johnson, Iv

A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to color a schematic graph of a parent cell to an equilibrium state. An operation is then performed to recolor nets connected to first and second child cells having the same device value within the parent cell, using a net coloring operation that recolors a first plurality of symmetric pins of the first child cell and recolors a second plurality of symmetric pins of the second child cell. Distinct device values are then generated for the first and second child cells by determining a first product of the colors of the recolored first plurality of symmetric pins and a second product of the colors of the recolored second plurality of symmetric pins. The operations to recolor the nets preferably include coloring a first pin of a child cell within a parent cell using a pin coloring operation that is a function of a device value of the child cell and a color of each of the pins of the child cell that are independently swappable with the first pin, but is independent of a color of a second pin of the child cell that is dependently swappable with the first pin.

Methods, apparatus and computer program products that perform layout versus schematic comparison of integrated circuits using advanced pin coloring operations

Layout versus schematic (LVS) comparison tools that use advanced symmetry resolution techniques

A layout versus schematic (LVS) comparison tool performs layout versus schematic comparison of integrated circuits having memory cells and non-memory cells therein. These operations are particularly useful when the integrated circuit layout includes one or more arrays of memory cells (i.e., bit cells) that are identified at a transistor level in the layout netlist. Such operations include scanning a layout netlist of the integrated circuit at the transistor level to identify a first device therein that has an identifiable characteristic associated with the plurality of memory cells relative to the plurality of non-memory cells. Upon detection of the identifiable characteristic, the layout netlist of a first memory cell containing the first device is traced in order to identify a first bit line and/or a first word line therein that is electrically coupled to the first memory cell. This tracing operation preferably comprises tracing a netlist path extending from the first device to a first bit line or a first word line electrically connected to the first memory cell. This netlist path may include a path defined by one or more nets and devices connected together and preferably connected between the first device and the first bit line (or first word line). The first bit line and/or first word line is then traced locally to identify a plurality of additional memory cells electrically coupled thereto along a column or row. Additional bit lines and words lines that are connected to these identified memory cells can also be traced in a similar manner to identify a plurality of rows and columns of memory cells in a memory array block.

Methods, apparatus and computer program products that perform layout versus schematic comparison of integrated circuit memory devices using bit cell detection and depth first searching techniques

Methods, apparatus and computer program products that perform layout versus schematic comparison of integrated circuits using advanced symmetry resolution techniques

A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to generate color symmetrizing matrices corresponding to respective child cells in the integrated circuit schematic. Here, the child cells are characterized as having a number of symmetrical configurations which at a port level are electrically equivalent. Operations are also performed to generate a first color symmetry vector for a child cell in the integrated circuit schematic and a second color symmetry vector for the corresponding child cell in the integrated circuit layout. A vector equivalency is also preferably determined by comparing a product of the color symmetrizing matrix and the first color symmetry vector against a product of the color symmetrizing matrix and the second color symmetry vector. Notwithstanding the presence of a vector equivalency, a possibility may still exist that with respect to the corresponding symmetric child cells in the schematic and layout, isomorphism between the schematic and layout is not present. To address this possibility, an operation is preferably performed to detect the absence of a spurious symmetry in the color symmetrizing matrix. If an absence is detected, the presence of the vector equivalency will unequivocally establish the one-to-one correspondence with respect to the child cells being analyzed. Thus, the need to perform a computationally expensive membership test to determine whether a selected permutation can be derived from valid symmetries, can be successfully eliminated. The preferred comparison tool also infers symmetries, where available, so that symmetries of a child cell may be propagated to a parent cell when the tool is evaluating a grandparent cell containing the parent cell.

Methods, apparatus and computer program products for determining

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Durham, NC, United States of America

Gary Bruce Lipton