Teletype Corporation

At&t Teletype Corporation

American Telephone and Telegraph, Co.

Gary B Ollendick

James M Berry

Kurt E Knuth

Anthony J Hauser

George Heckel

Barry H Jacksier

An analog to digital interface circuit includes two matched, symmetrical, differential amplifiers which in response to an analog signal having a rising edge and a falling edge produce first and second output signals which are identical but 180.degree. out of phase; whereby the rising edge of the analog signal corresponds to the rising edge of the first output signal, the falling edge of the analog signal corresponds to the rising edge of the second output signal and the time interval between the rising edges of the two output signals is equal to the time interval between the rising and falling edges of the analog signal. The outputs of the differential amplifiers are further processed by two matched, symmetrical buffers which produce first and second digital signals having like falling edges corresponding to the rising and falling edges of the analog signal, respectively. Control pulses generated off the like edges of the two digital signals are used as inputs to digital logic to reconstruct the analog signal or generate clock pulses.

Analog to digital interface circuit

An adjustable time delay circuit 10, 50 includes a time delay line 12 including a plurality of series connected time delay units 18a-p. During adjustment, sampled signals along the delay line 12 are compared with a reference signal by NOR-gates 22e-m. Upon a comparison being attained, the output of the corresponding NOR-gate 22e-m sets a selected flip-flop 30e-m which in turn routes the signal at a selected delay line tap 38e-m through a NOR-gate 34e-m to an output OR-gate 40. The tap 38e-m selected, compensates for component propagation characteristics thus maintaining a predetermined time delay through the time delay circuit 10.

Adjustable time delay circuit

A digital receiver (40) includes a differential amplifier (42) providing data signal E and a control signal F. The level of the control signal F is related to the average level of the data signal E. A slicing circuit 44 includes series connected transistors (46, 48), the gates of which receive the data signal E. A third transistor (52) is connected to provide hysteresis to the slicing circuit, and a fifth transistor (54) is connected in parallel with the third transistor (52). The control electrode of the transistor (52) receives the control signal F from the differential amplifier (42).

Receiver for digital signals

A cache memory 30 having a thirteen bit word length is illustrated for storing more than one data word read from a system memory 80 having an eight bit word length and providing the stored words to a video display 18 on a reoccurring basis. The cache memory 30 has a storage capacity sufficient to store the words for one row of display text characters. Two system memory bytes are concatenated by a latch 74 and storage buffer 96 prior to writing into the cache memory 30. After the scanning of the first word of the last scan line in the current cathode ray tube (19) display text row, the first word of the new text row is written into the cache memory (30) from the system memory (80). The write procedure is completed before the last word of the new text row is read from the cache memory 30 to the cathode ray tube display 19 during the writing of the first scan line of the new text row.

Cache memory and control circuit

A digital voltage comparator is illustrated including a cross-coupled latch 10 having input nodes 12 and 14. After the input nodes 12 and 14 of the latch 10 have been respectively preloaded to the input A and reference E voltage levels during the active state of clock phase .phi..sub.1, the latch is allowed to arrive at a stable state during the active state of clock phase .phi..sub.2. Thereafter, when clock phase .phi..sub.3 is active, the output of the latch 10 is coupled to the input of a single stage shift register 20. The output of the shift register 20 is fed to inverters 22 and 26 and through a voltage divider for preloading the node 14 of the latch 10 during the next active state of clock phase .phi..sub.1.

Digital voltage comparator

A paper web is maintained on a rotating apertured drum by means of a vacuum created inside of the drum. The paper length is slightly greater than the circumference of the drum thereby providing a tangentially projecting flap which is detected by a flap sensor. The concurrance of a pulse from the flap sensor with an end of message signal enables a counter. A first series of selected states of the counter are decoded and used to interrupt the vacuum causing the paper to come to rest against a shroud surrounding the drum. A second series of counter states, some of which coincide with the first series, open a discharge door covering a paper discharge opening in the shroud. When the vacuum is reapplied to the drum, upon expiration of the first series of counter states, the rotating drum boosts the paper out through the discharge opening.

Method and apparatus for removing paper from a rotating drum

A circuit for controlling a graphic display printer wherein a paper sheet is wrapped about a rotating drum and maintained in place thereon by a vacuum. The length of the paper sheet is slightly longer than the circumference of the drum and thus defines a tangentially projecting flap. A sensor detects passage of the flap and in response to the initial detection, a counter is started having a cycle corresponding to one rotation of the drum. Selected states of the counter are digitally compared to the output of the flap sensor. After the rotational position of the flap has been determined twice for each of three successive drum revolutions, a paper validation signal is generated indicating that the paper is properly wrapped about and rotating with the drum. In response to the validation signal, printing is started. The circuit also includes means for preventing writing on the flap by correctly locating the copy with respect to top of paper and for maintaining a straight, first, print line irrespective of the characteristics of the paper edge or its positional sensing variations.

Method and apparatus for controlling a web handling device

An ink jet printer in which refined half-tones or shades of gray are produced while retaining high contrast capability using a dot matrix in which the dots are of the same density for the same shading plus or minus one drop of ink at selected dot locations within the matrix but with each dot being printed in response to an individual shading density or darkness input signal.

Growing community of inventors

Mundelein, IL, United States of America

Gary B Ollendick