Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Ciphermax, Incorporated

Sgs-thomson Microelectronics Limited

Gary B Kotzur

William J Walker

Dale J Mayer

Michael L Witkowski

Patricia E Hareski

Mohammad A Khan

Sompong Paul Olarig

John Erven Jenne

Siamak Tavallaei

Gregory T Chandler

Mark Lyndon Oelke

Kirk D Roller

David F Heinrich

Alan L Goodrum

Charles D Waggoner

Matthew John Schumacher

Jeffrey T Wilson

Roger Richter

Kurt C Lantz

Richard J Blumberg

A switch fabric system comprises a first chassis for receiving a plurality of line cards each having a plurality of ports and at least two switch fabric cards wherein each line card comprises a plurality of link ports for linking the line card with the switch fabric card. Each switch fabric card provides a switching bandwidth. The system comprises a management unit for managing the traffic on the switch fabric cards wherein the management unit removes the traffic from one switch fabric card if the one switch fabric card is to be removed while the other switch fabric card operates and transfers the traffic to the other switch fabric card.

System and method for expansion of computer network switching system without disruption thereof

A network communication device including port control circuitry for controlling packet flow between the ports of the device, where the port control circuitry includes a port manager that directs packets between the ports and port bonding circuitry that bonds two or more of the ports into a bonded port set. For each packet to be sent via the bonded port set, the port bonding circuitry selects one of the bonded ports for transmitting the packet. More than one bonded port set may be defined in a given communication device, and each bonded port set may include from two ports up to all the ports of the device, as long as each port is included in only one bonded port set. One or more port bonding registers are provided to identify which of the plurality of ports are bonded in each bonded port set. In one embodiment, the bonded ports are selected on a packet by packet basis so as to achieve a relatively even distribution of packets sent by each bonded port. In an alternative embodiment bonded ports are assigned to packet source identifiers so as to achieve a relatively even distribution of source identifiers among the bonded ports. If bonded ports are assigned to particular source identifiers, then the traffic is preferably monitored and the assignments are periodically adjusted to achieve even distribution of packet flow on the bonded link. The bonded ports may have different bandwidths, in which case traffic is distributed on a proportionate basis.

Network communication device including bonded ports for increased bandwidth

A heterogeneous and scalable bridge capable of translating a plurality of network protocols is adapted for coupling to a network switch fabric. The bridge uses at least one egress buffer interface and can perform port aggregation and bandwidth matching for various different port standards. The bridge is adapted for both networking and storage area networking protocols. A control unit is implemented with the bridge is able to identify control and flow information from different protocols and adapt them to the respective interface to which they are to be transmitted. Accounting logic is provided to one or more of the elements of the apparatus to aid in the tracking, storing, and reporting of network traffic.

Network processor interface system

A network switch includes a plurality of first network ports coupled to a first bus, a plurality of second network ports coupled to a second bus, a bridge interface enabling data transfer between the buses, a switch manager controlling the flow of network data, and a processor for performing supervisory and control functions. The first and second network ports operate according to different network protocols, and the first and second buses operate according to different bus standards. During packet data transfers across the first bus, the bridge interface emulates a first network port. During packet data transfers across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports, thus relieving the processor of performing overhead functions associated with data transfers across the second bus.

Network switch with a multiple bus structure and a bridge interface for transferring network data between different buses

A programmable arbitration system including control logic to select one of several arbitration schemes for selecting the ports of a network switch, a memory to store priority values indicating the relative priority of each of the ports, monitor logic to monitor each of the ports and to program the priority values in the memory based on a priority scheme selected by the control logic, and arbitration logic to select a port having the next highest priority. The arbitration schemes preferably include a round-robin priority scheme, a first-come, first-served (FCFS) priority scheme, a weighted priority scheme, or any other desirable priority scheme. The monitor logic includes polling logic to periodically poll the ports and to program a priority value of each port. The memory includes receive and transmit lists to indicate of which of the ports have indicated needing service and a corresponding priority value. The arbitration logic includes a receive arbiter and a transmit arbiter, each of which use a corresponding arbitration count.

Programmable arbitration system for determining priority of the ports of a network switch

A network switch including one or more network ports for receiving and transmitting data is disclosed. The network switch also includes a processor, a switch manager, and memory. Each port includes a network interface, a data bus interface, and a processor port interface. A data bus is coupled to the data bus interface of each of the ports and the switch manager. A processor bus is coupled to a processor, the switch manager, and to the processor port interface of each of the ports. A memory bus is coupled to the memory and the switch manager. The switch manager periodically polls each of the network ports to determine the status of each port. The switch manager controls the flow of data between the network ports and memory based on the port status. The separate processor bus allows the processor to perform overhead functions, such as monitoring, determining status and configuration, without consuming valuable data bus bandwidth.

Network switch including a switch manager for periodically polling the network ports to determine their status and controlling the flow of data between ports

A network switch including a central memory that stores device identification information, port numbers, control information, and packet data received at the ports of the switch. The memory includes a packet section that stores packet data and a device identification section that stores identification entries, where each entry corresponds to a network device coupled to a port of the switch. The switch includes a switch manager to control data flow between the ports and the central memory. Each of the identification entries includes a unique network address to identify one of the network devices and a port number to identify one of the network ports. Each of the identification entries is located within the central memory at a hash address derived by hashing the unique network address. Hash logic receives and hashes each network address to determine a hash address, which is used to access the identification entries. The memory is organized into a chain structure to enable quick access of entries. The switch manager further includes a control memory for storing control registers, including a freepool control register for identifying a freepool chain of memory sectors, a receive control register for identifying a corresponding receive sector chain and a transmit control register for identifying a corresponding transmit packet chain for each of the ports.

Network switch with shared memory system

A network switch including a plurality of network ports for receiving and transmitting data, where each port includes at least one statistics register for storing statistics information, such as Ethernet statistical and configuration information. The switch also includes a switch manager, which further includes a memory, retrieval logic for detecting a statistics request signal and for respondingly retrieving the statistics information for storage in the memory, and response logic for asserting a statistics response signal after the statistics information is stored. A processor is coupled to the switch manager through a bus, where the processor asserts the statistics request signal and then detects assertion of the statistics response signal. Upon detecting the response signal, the processor retrieves the statistics information from the memory. In this manner, the processor is removed from direct connection to the statistics registers and free to complete other tasks while the information is being gathered by the switch manager, thereby increasing the efficiency of the processor and of the network switch. Each port preferably includes a network interface, a processor port interface for enabling the switch manager to retrieve the statistical information, and a data bus interface for network traffic. The switch manager thus includes two separate bus connections to each of the ports, so that statistical reads do not interfere with network data packet flow.

Network switch with statistics read accesses

A system for performing concurrent read and write cycles in a network switch. The network switch includes several network ports, a data bus and a switch manager to execute a concurrent read and write cycle on the data bus by asserting a first port number to identify a source port followed by a second port number to identify a destination port. Each of the ports includes a network interface for sending and receiving data packets and a data interface to store the first port number, to assert data received from the network interface onto the data bus if that port is identified by the first port number, and to retrieve data from the data bus for transmission by the network interface if that port is identified by the second port number. In this manner, data is transferred directly between a source and a destination port without being buffered in the switch manager. The bandwidth of the data bus is increased since data is transferred only once on the data bus. Latches are provided for the ports to latch the read port number to allow that write port number to be asserted during the cycle. A method of executing a concurrent read and write cycle includes the steps of asserting a first port number to identify a source port, latching the first port number, asserting a second port number to identify a destination port, and concurrently writing and reading the data on the data bus.

Method and system for performing concurrent read and write cycles in network switch

A network switch including a plurality of network ports for communicating data packets, each port including logic for receiving a backpressure indication and for transmitting a jamming sequence to terminate transmission of a data packet being received. The switch includes a memory for temporarily storing data packets received by the ports, and a switch manager for determining one or more threshold conditions of the memory, for determining if a new data packet being received is to be stored in the memory for transmission by another port, and if so, for providing the backpressure indication to terminate the new data packet if a backpressure signal indicates that a threshold condition would be violated by storage of the new data packet. The jamming sequence is not sent if the packet is not intended to be stored in the switch, so that network devices coupled to a single port may continue to communicate to each other. The remaining ports of the switch are not effected. The threshold conditions include, among others, a maximum number of sectors storing data packets received by a port in a receive sector chain, a maximum number of data packets stored in the memory in a transmit packet chain, a minimum number of free sectors available in the memory for storage of data packets, and a maximum number of broadcast data packets stored in the memory.

Network switch with dynamic backpressure per port

A network switch including a plurality of first network ports, a plurality of second network ports, a first bus, a second bus and a bridge interface coupled between the first and second buses. The first ports receive and transmit network data according to a first network protocol and the second ports receive and transmit network data according to a second network protocol. The first and second buses operate according to different bus standards. The bridge interface enables data transfer between the first and second buses and thus between the networks operating at different protocols. The switch includes a switch manager that controls the flow of network data and a processor for performing supervisory and control functions. The bridge interface includes receive buffers and transmit buffers assigned to respective ports. During packet data transfer operations across the first bus, the bridge interface emulates a first network port. During packet data transfer operations across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports. This processor is relieved of performing necessary overhead functions associated with the second bus and is thus freed to perform other important switch functions.

Network switch with a multiple bus structure and a bridge interface for

Programmable arbitration system for determining priority of the ports of

A network switch including a separate cut-through buffer for facilitating cut-through mode of data transfer. The switch further includes a data bus coupled to each of the ports, a memory and a switch manager coupled to the data bus and to the memory for controlling data flow. The switch manager includes a receive buffer for handling data received by the switch, a transmit buffer for handling data to be transmitted by the switch, and a separate cut-through buffer for receiving data at any of the ports and for buffering the data to another one of the ports during cut-through mode of operation. The switch manager includes status memory, which includes programmable receive and transmit mode values for each of the ports, the modes selecting between cut-through and store-and-forward mode of operation for an indicated direction for each port. Control logic operates source and destination ports in cut-through mode if the receive mode value of the source port and the transmit mode value of the destination port have both been programmed to select cut-through mode.

Network switch with separate cut-through buffer

Apparatus, and an associated method, for requesting initiation of generation of an interrupt at an I/O APIC (input/output advanced programmable interrupt controller) of a multi-processor computer system. Initiation of generation of the inter-processor interrupt is requested by a peripheral component device, such as a PCI bus controller, not directly connected to an APIC bus extending to interrupt controllers associated with each of the processors of the multi-processor computer system. The interrupt permitted to be initiated by the peripheral component device includes, inter alia, a remote read request.

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Harris County, TX, United States of America

Gary B Kotzur