International Business Machines Corporation

Gary B Hoch

Andrew Boyce McNeill, Jr

Douglas R Chisholm

Timothy Vincent Lee

Ed Wachtel

Timothy V Lee

Serafin J Garcia, Jr

Stephanie P Payne

Eric H Stelzer

Rex E McCrary

Donald G Williams

Daniel Petkevich

Hai V Pham

Michael S Gatson

An information handling system transfers command blocks between a host processing side having a host processing unit and a host memory and a local processing side having a local processing unit and a local memory. The command blocks are transferred from the host processing side to the local processing side by storing the host address of the command block in a local side register set. Upon storing the host address a transfer signal is given to a command block transfer controller to start a command block transfer without the local processor unit intervention.

Information handling system for transfer of command blocks to a local

An information handling system transfers command blocks between a host processing side having a host processing unit and a host memory, and a local processing side having a local processing unit and a local memory. The local memory includes a command address queue portion for queuing local command address images containing the local addresses of the command blocks. A command block transfer controller is responsive to the local command address images for storing the transferred command block into a corresponding portion of the local memory.

Information handling system having a local address queue for local

An information handling system transfers data blocks between a host processing side having a host processing unit and a host memory and a local processing side having a local processing unit and a local memory. The host memory includes a status queue memory portion having a plurality of status queue images each image storing a status information relating to a corresponding data transfer. The status information relating to data block transfers are posted on the host processing side. The host processing unit, upon system initialization, sets up a status queue register set within the local processing side defining status queue parameters including the location of the status queue memory portion within the host memory and pointer values pointing to where status queue images are to be stored and from where they are to be retrieved.

Status handling for transfer of data blocks between a local side and a

An information handling system transfers data blocks between a host processing side having a CPU and a host memory and a local processing side having a local processing unit and a local memory. The local memory includes a DCB queue memory portion having a plurality of DCB images each image defining host and local addresses of a corresponding data transfer. The DCB images also store a default status condition representing the most likely condition of a data transfer which in the preferred embodiment is a no error condition. A data transfer status detector determines whether the default status condition is true or false. If true, the default status information relating to a corresponding data block transfer is posted on the host processing side without local processing unit intervention.

Information handling system using default status conditions for transfer

A high performance serial bus operating at multiple transmission rates is disclosed. The serial bus is able to automatically generate data response packets for return to a requesting node. The automatic packet generation uses the source and destination information to generate a return destination packet for directing the requested data to the request source destination. Since the bus network is capable of operating at several different transmission rates, the speed at which the data request packet was transmitted is used for retransmitting the data requested back to the source node requesting the data.

System for reformatting a response packet with speed code from a source

A computer system allows for a hardware structure to participate in the transmission of P1394 packets, which are comprised of command or data blocks from linked list structures in a system memory, is disclosed. The system is able to provide dynamic appending of these command or data blocks to the link list while they are being operated upon. This provides an efficient transaction layer operation, which minimizes signalling between the link list operator or control code, and other hardware features.

Method and system for dynamically appending a data block to a variable

DMA adapters which perform programmed data transfer operations in response to descriptors are programmed by information in the same descriptors (and adapter logic responsive to that information) to perform various ancillary control functions relative to addressable I/O devices that conventionally would be addressed and controlled directly by a host (higher level) system processor (e.g., the processor that prepares the descriptors). The ancillary control functions are variable programmably in number (e.g., in the disclosed embodiment, one descriptor can define 0, 1 or 2 discrete ancillary control operations) and effects produced by each operation are programmably variable (e.g., ancillary operation can be used by the adapter to alter states of addressed devices; for example, to prepare a device that has been transferring data in one direction, in a half-duplex mode, for transferring data in the opposite direction, or to switch to a full duplex mode, etc.). These functions hitherto have imposed significant processing burdens on the host processor and functional constraints on the adapters and devices; typically, constraints requiring the adapter and one or more devices to be idled for the time required by the host to condition the device(s). Accordingly, delegation of these functions to the adapter, allows them to be carried out without idling of any system elements and while the host is otherwise productively occupied. Also, such delegation creates new applicational possibilities; e.g., having an adapter linked to a communication channel react to remotely originated signals and set up operations tightly coordinated in real time to previously executed operations (for example, retransmission of data previously received with detected error).

Computer I/O adapters for programmably varying states of peripheral

A processor stores descriptors without explicit linkages, in non-contiguous memory locations, and sequentially hands them off to an adaptor which manages scheduling and processing of data transfers defined by the descriptors. Each descriptor is handed off in a request signalling process in which the processor polls the availability of a request register in the adaptor, and writes the address of a respective descriptor to that register when it is available. The adapter then schedules processing of the descriptor whose address is in the request register. The adapter manages a 'Channel Descriptor Table' (CDT), which defines the order of processing of descriptors designated by the requests. In effect, the CDT defines a linked list queue into which the adapter installs descriptors, in the sequence of receipt of respective requests. Using the CDT information, the adapter retrieves successively queued descriptors and controls performance of operations (data transfer or other) defined by them. Accordingly, descriptors in the queue are retrieved and respectively defined operations are performed, in the order of receipt of respective requests; as if the descriptors had been stored by the processor with explicit linking and chaining associations and handed off to the adapter as an explicitly chained set of descriptors. In a preferred embodiment, a 'multichannel adapter unit' (MAU), directing data transfers relative to multiple channels, contains one request register for all channels and a separate CDT and 'request address port' dedicated to each channel. Requests accompanied by addresses designating these ports are 'funneled' through the request register to CDT queues of respective channels. The processor can effectively remove a descriptor from any CDT queue, without potentially compromising handling of data transfers defined by other descriptors in the queue, by writing a 'skip code' to the descriptor. Upon retrieving a descriptor with a skip code, the adapter automatically skips the operation defined by that descriptor and chains to a next descriptor (if the queue defined by the CDT is not empty).

Growing community of inventors

Coral Springs, FL, United States of America

Gary B Hoch