Arm Limited

International Business Machines Corporation

Gary Alan Gorman

Lee Evan Eisen

Daniel Arulraj

Neil Burgess

Robert Alan Cargnoni

Charles Francis Marino

Graeme Peter Barnes

Julie Ann Rosser

Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising an ordered plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with the vector positions; predicate generation circuitry to apply a processing operation to generate an ordered set of predicate indicators, each associated with a respective one of the vector positions, the ordered set of predicate indicators being associated with an ordered set of active indicators each having an active or an inactive state; and a detector to detect a status flag indicative of whether a predicate indicator at a position, in the ordered set of predicate indicators, corresponding to the position of an outermost active indicator having the active state, has a given state; in which the detector comprises: first and second circuitry to combine the ordered set of predicate indicators and the ordered set of active indicators using first and second respective logical bit-wise combinations to generate first and second ordered sets of intermediate data; and arithmetic circuitry to combine the first and second ordered sets of intermediate data using an arithmetic combination generating a carry bit, the detector generating the status flag in dependence upon the carry bit.

Data processing apparatus and method for generating a status flag using predicate indicators

Processing circuitry selectively applies vector processing operations to one or more data items of one or more data vectors. Each data vector comprises a plurality of data items at respective vector positions in the data vector according to the state of respective predicate indicators associated with the vector positions. Predicate generation circuitry apply a processing operation to generate a set of predicate indicators, each associated with a respective one of the vector positions, to generate a count value indicative of the number of predicate indicators in the set having a given state, and to store the generated set of predicate indicators and the count value in a predicate store.

Predicate indicator generation for vector processing operations

A data processing apparatus is provided, for performing a determination of whether a value falls within a boundary defined by a lower limit between 0 and 2and an upper limit between 0 and 2. The apparatus includes storage circuitry that stores each of the lower limit and the upper limit in a compressed form as a mantissa of q&#x3c;m bits and a shared exponent e. A most significant m-q-e bits of said lower limit and said upper limit are equal to a most significant m-q-e bits of said value. Adjustment circuitry performs adjustments to the lower limit and the upper limit in compressed form and boundary comparison circuitry performs the determination on the value using the lower limit and the upper limit in the compressed form.

Bounds checking

A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The processor distributes data on-ramps and data off-ramps across the data lanes of a data trunk of the primary interconnect trunk to enable communication with compute elements and other structures both on-chip and off-chip.

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Austin, TX, United States of America

Gary Alan Gorman