Amdahl Corporation

Gary A Woffinden

Donald L Hanson

Gene M Amdahl

Joseph A Petolino, Jr

Ronald K Kreuzenstein

Theodore S Robinson

Gwynne L Roshon-Larsen

Eugene T Wang

Mark Semmelmeyer

Joseph A Petolino

Stephen S Si

Jeffrey A Thomas

Christopher D Finan

James P Millar

Ajay K Shah

Robert A Ertl

Shen H Wang

Gregory Aldrich

A clock distribution system for reducing clock skew between tightly coupled central processing units in a multi-processor system. The multi-processor system includes (1) a configuration processor for generating a first configuration signal and a second configuration signal, a first clock, a second clock, (2) a first processor having a first central processing unit, (3) a second processor having a second central processing unit, (4) a first clock generator for generating a first delayed clock signal from the first or second clock in accordance with the configuration signals, and (6) a second clock generator generating a second delayed clock signal from the first or second clock in accordance with said configuration signals. The clock distribution system comprises a distribution means for receiving the first delayed clock signal, the second delayed clock signal and the configuration signals, and for distributing in accordance with the configuration signals either the first delayed clock to the first central processing unit and the second delayed clock to the second central processing unit, or the first delayed clock signal to both the first and second central processing unit or the second delayed clock signal to both the first and second central processing unit.

Clock distribution system for reducing clock skew between processors in

A computer system architecture implementing multiple central processing units, each including a split instruction and operand cache, and that provides for the management of multiple copies (line pairs) of a memory line through the use of a line pair state is described. Systematic management of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture implements the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the instruction and operand cache buffers of a single central processor. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depending on whether the operand buffer destination is a memory line that is a member of a line pair.

Computer system architecture implementing split instruction and operand

The reporting of errors that are detected when data which contains an error is moved from a high speed buffer memory array to a main storage array is deferred so that the error checking and correcting logic associated with the main storage memory array will recognize the data as containing an error generated in the buffer array and report the error only when the data is moved out of the main store. In this manner, a process relevant to the erroneous data is assured to be in operation when the error is reported.

Apparatus for storing data with deferred uncorrectable error reporting

A data storage system includes a translation buffer for translating virtual page addresses to system page addresses, a data cache in which the data is identified by virtual address, and a mainstore in which data is stored by system address. When a new translation buffer entry is made which replaces an old translation buffer entry and both the old and the new translation buffer entries translate to the same system page address, then all data residing in the data cache identified by the virtual page address of the old translation buffer entry is allowed to match the virtual page address of the new translation buffer entry, and need not be evicted. This provides efficient handling of synonymous virtual addresses.

Virtual memory system having identity marking for common address space

Access control to a high speed data buffer in a data processing machine is bypassed in order to enhance the speed of access of data which must be retrieved from a large capacity main storage facility without requiring additional circuitry in the data processing machine. Access control normally requires an entire line of data to be present in a cache before allowing a read to a portion of the line. When lines are moved in to the cache, only sub-line increments are loaded at a time. Thus, when a line is being moved in from a main store to the cache, the increment that satisfies a pending request for access is transferred first. The access control is overridden to allow access to the increment before the balance of the line is transferred.

Apparatus for buffer control bypass

A memory apparatus which includes an intermediate store addressed by logical addresses and a main store addressed by system addresses. The memory unit has a translator for translating logical addresses to system addresses. The translator includes a translation lookaside buffer having a system address store with first and second fields storing system addresses corresponding to each translated logical address and a control field including a flipper bit for indicating which one of the system addresses is the currently active real address. The control field also includes an eviction pending bit for each system address field. When the TLB is updated with a new translation, the previos active address field is marked with an eviction pending bit and the the previos inactive address field is written over with the new translation and marked active. After eviction from the intermediate store of data relying on the system address marked eviction pending, the eviction pending bit is turned off, freeing the space for subsequent new translations.

Eviction control apparatus

In a data processing system having a main store addressed by system addresses and a buffer addressed by logical addresses, where more than one logical address may map to a single system address, a translation buffer is adapted to provide a means for linking translation buffer locations that may map to a given system address to identify all synonym logical addresses. The implementation includes a list header table that generates a pointer to the translation buffer in response to a system address. A search of the translation buffer beginning at the location identified by the list header table and proceeding through each linked location is carried out to identify all synonym logical addresses. The synonym logical addresses are associated by an exclusive ordered list and a means is provided for updating the exclusive list when new entries are made in the translation buffer or old entries are deleted.

Apparatus for enhancing searches of data tables

A data processing system includes virtual-addressed and real-addressed stores. Whenever an addressed location is not resident in the memory in which it is attempted to be accessed, the address is translated to the other address space. If a virtual address cannot access the desired location in the virtual memory the virtual address through a virtual-to-real translator is translated to a real address and the location is addressed in the real memory. Whenever a real address needs to access a virtual address in the virtual-addressed memory, the real address is converted through a real-to-virtual translator in order to locate corresponding locations in the virtual-addressed memory. Virtual-to-real translation is carried out by storing the real addresses corresponding to a virtual address in a translation lookaside buffer. Entry to the translation lookaside buffer is gained by using a TLB pointer in a tag array which points to the TLB address which contains the desired real address. By storing a TLB pointer in the tag array rather than storing the full address, many bits are saved in the tag array.

Data storage unit employing translation lookaside buffer pointer

An apparatus translates a set of logical addresses to a system addresses where the set of logical addresses includes virtual and real addresses which map to the same system address. An address mechanism provides a requesting field for indicating when a requesting logical address is virtual or when a requesting logical address is real. An address translator translates logical addresses to system addresses. A translation buffer stores translation information for associating logical addresses with system addresses. The translation buffer includes means for storing a resident field for indicating if stored translation information associates a virtual address with a system address, a real address with a system address, or both a real address and a virtual address with a system address.

Translation of virtual and real addresses to system addresses

Present invention presents a novel mechanism for reducing the amount of storage space necessary to perform error checking and correcting in a storage unit of a data processing machine by utilizing the information present in the parity checking portion of the storage unit. The novel mechanism is based on generating an error checking and correcting code which includes a first portion identifiable by parity bits normally stored with data words in a data storage device and a second portion. The second portion contains fewer bits than required in the prior art for an equivalent level of error checking and correcting and only the second portion is stored. When data is moved out of the storage device, the first portion is identified from the parity bits.

Apparatus for reducing storage necessary for error correction and

A memory system which comprises a mainstore for storing lines of data and a buffer store for storing lines of data that are a subset of the data stored in the main store. The buffer store is comprised of a plurality of associativities. A line of data stored in the buffer having a given address may be stored in any one of the plurality of associativities. A tag store stores a tag for the associativities. A field from a buffer store address is compared with the stored tag in the tag store to produce a data selection signal for selecting from among the plurality of associativities the proper line of data. When the buffer has only two associativities, a bit in the buffer store address which has different values for the two associativities is tested, and thus the proper line of data is selected. The bit position is indicated by a pointer stored in the tag array. A selection of one of two data lines is made prior to a determination of the presence or validity of data in the buffer store.

Addressing system for an associative cache memory

An apparatus for enhancing the speed of access of an execution unit in a data processing machine to the high speed buffer memory array by storing data from the execution unit in the buffer before completing error checking operations.

Apparatus for fast data storage with deferred error reporting

Disclosed is a data processing system including virtual-addressed and real-addressed stores. One store is addressed with real addresses and the other store is addressed with virtual addresses. Whenever an addressed location is to be accessed in a store addressed by the other type of addresses, the address is translated to the other type of address. If a virtual address cannot access the desired location in the virtual store, the virtual address through a virtual-to-real translator is translated to a real address and the location is addressed in the real store. Whenever a real address needs to access a virtual address location in the virtual-addressed store, the real address is converted through a real-to-virtual translator in order to locate corresponding locations in the virtual-addressed memory.

Virtually addressed cache

Disclosed is an apparatus for storing data wherein there are at least two storage units which are addressed by different addressing schemes. The primary storage unit is addressed with a unique addressing scheme while the other storage units are addressed with a scheme wherein more than one of the other addresses may map to a single unique primary address. The apparatus for storing data includes a mechanism for translating all of the unique primary addresses to all of the other addresses which map to that unique primary address.

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Scotts Valley, CA, United States of America

Gary A Woffinden