Vlsi Technology, Inc.

Other

Freescale Semiconductor,inc.

Qualcomm Incorporated

Honeywell G.m.b.h.

Gary A Walker

Ned D Garinger

Martin L Dorr

Mark W Naumann

David R Evoy

Gary D Hicok

Lonnie Calvin Goff

Franklyn H Story

Joseph Alan Thomsen

James C Steele

James J Jirgal

Peter Chambers

Nicholas Julian Richardson

David K Cassetti

David P Norton

Scott L Gray

Rishi Nalubola

Michael R Crews

William Demmer

Tom Ricks

Samuel Steigerwalt

Igor Prilepov

Robert Overholt

Clarence Underwood

Bruce E Cairns

Collin Walker

Mike Crews

Nikhil Bhatia

Edward Demmer

Neil L Sampson

A programmable pill box assembly includes a pill box that has a plurality of compartments therein for containing pills. A plurality of doors is each hingedly coupled to the pill box. Each of the doors is aligned with a respective one of the compartments for opening and closing the compartments. A sensing unit is coupled to the pill box to sense when each of the doors is opened or closed. A transmission unit is removably coupled to the pill box and the transmission unit transmits an alert signal when the sensing unit senses that a respective one of the doors has not been opened at a predetermined time. A bracelet is worn on a wrist of the user and the bracelet is in wireless communication with the transmission unit. The bracelet vibrates to remind the user to take the pills in one of the compartments in the pill box.

Programmable pill box assembly

The present invention relates to methods and apparatuses for eliminating or mitigating the effects of the corruption of contents in an external flash memory, such as that which can occur during a power interruption. Embodiments of the invention include methods to log external flash memory program and erase operations redundantly to dedicated buffer partitions in the flash memory itself. The log information from external serial flash memory is used to erase the sector that was being programmed or erased when power was removed. According to certain aspects, the redundant storage of log information in embodiments ensures that if one version of the log information is corrupted, the other version can be used.

Method and apparatus for managing corruption of flash memory contents

Systems and related methods for controlling vehicle position and movement are disclosed. A system includes one or more computers configured to receive data corresponding to video image frames of at least a portion of a course, and analyze the video image frame to estimate at least one of position and orientation of the vehicle within the course. A method includes identifying groups of pixels from the video image frames that are determined to correspond to non-background objects in the course. The method also includes correlating at least a portion of the identified groups of pixels with known objects in the course, and analyzing positions of the groups of pixels within the video image frames and known positions of at least one of an image capture device and known objects relative to the course to estimate at least one of the position and orientation of the vehicle within the course.

Systems and methods for controlling vehicle position and orientation

A vehicle turn signal canceling system with means to recognize that a quantified turn has been made in order to deactivate the signaling condition. The system includes a microcontroller and an inertia sensor which measures the lateral or side force created when the vehicle turns left or right. The automatic function cancels the turn based on the side force as follows: at the time the turn signal is activated, the system records the referenced lateral or side force (the 'reference point'); second, when the side force exceeds the reference point, plus a pre-determined side force, the unit accumulates exceedance time; and third, when the exceedance time reaches a pre-determined period of time, the turn signal status is then changed to 'cancel' and the signaling condition is deactivated.

Automatic cancellation means for vehicle turn indicator signals

An inflation device and method for inflating or deflating inflatable objects, such as game balls is disclosed. The inflation device measures the pressure of a game ball and inflates or deflates the ball to a pressure selected by the user. Also disclosed is an injection apparatus that can be used to automatically retract an injection needle from the game ball or other inflatable object.

Inflation device

An OCN for integrated processing elements including a network with multiple ports and multiple port interfaces. The ports and the port interfaces conform to a consistent port protocol. Each port interface converts information between bus transactions of a corresponding processing element and network packets and exchanges network packets with other port interfaces. Each port includes an arbitration interface and a data interface and the network includes an interconnect and an arbiter. The interconnect includes selectable data paths between the ports for packet datum transfer. A port source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. A port destination interface receives packet datums via available input buffers. Each transaction request includes a transaction size and a destination port address. The arbiter receives transaction requests, arbitrates among transaction requests, provides acknowledgements and controls the interconnect to select data paths between sources and destinations.

On chip network

A network that maximizes interconnect utilization between integrated processing elements, including ports, an interconnect, port interfaces, and an arbiter. Each port includes arbitration and data interfaces. The interconnect includes selectable data paths between the ports for packet datum transfer. Each port interface includes processing, source and destination interfaces. The source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. The destination interface receives packet datums via a number of available input buffers. Each transaction request includes a transaction size, a packet priority, and a destination port address. The arbiter includes a request queue and a buffer counter for each port and a datum counter for each acknowledged transaction. The arbiter arbitrates among transaction requests based on a selected arbitration scheme, destination buffer availability, data path availability, and priority, and uses the packet datum counters, arbitration latency and data path latency to minimize dead cycles in the interconnect.

On chip network that maximizes interconnect utilization between processing elements

An OCN with independent logical and physical layers for enabling communication among integrated processing elements, including ports, bus gaskets and a physical layer interface. Each bus gasket includes a processor element interface and a port interface. Each processor element interface of at least two bus gaskets operates according to a first logical layer protocol. Each port interface operates according to a consistent port interface protocol by sending transaction requests and receiving acknowledgements and by sending and receiving packet datums via the corresponding port. The physical layer interface transfers packets between the ports and includes an arbiter and an interconnect coupled to each port. Additional bus gaskets may be added that operate according to a second logical layer protocol which may or may not be compatible with the first. Any bus gasket may be added that is configured to communicate using multiple logical layer protocols.

On chip network with independent logical and physical layers

A scalable network for supporting an application using processing elements including ports, an interconnect, port interfaces, and an arbiter. Each port conforms to a consistent port interface protocol regardless of number of ports, frequency of operation, maximum datum width or data path concurrency. The interconnect has a scalable maximum datum width and a scalable data path concurrency, and includes selectable data paths between any two ports to enable transfer of datums between the ports. Each port interface formulates packets for transmission and receives packets via the corresponding port and the interconnect, where each packet includes one or more datums. The arbiter controls packet transfer via the interconnect between source and destination ports. The interconnect has a scalable data path concurrency. Pipeline stages may be added to support a selected clock frequency. The OCN may be a component library including bus gasket, interconnect and arbiter components.

Scalable on chip network

A network with memory device address decoding that enables communication among integrated processing elements, including a network, a processing element and a bus gasket. The network transfers packets between multiple ports, where each port conforms to a consistent port interface protocol. The processing element includes a bus and a memory device programmed with the address of each port, so that a transaction on the bus indicating another port is decoded by the memory device. The bus gasket includes a bus interface that generates packets and a port interface that sends and receives the packets according to the consistent port interface protocol and that uses the decoded address as a destination port address. The memory device may be implemented in any desired manner, such as a memory management unit (MMU) or a direct memory access (DMA) device.

On chip network with memory device address decoding

The present invention relates to a system and method for supporting DMA I/O devices. A PCI-PCI bridge is provided to support DMA I/O devices on the PCI bus. Through the use of two signal lines and a serial link, DMA transfers may be accomplished over the PCI bus. A PCI-ISA dock bridge is also provided to allow the system to support DMA I/O devices and ISA masters (i.e., any device including DMA I/O devices on the ISA bus that generates ISA cycles) on the ISA bus.

System for supporting DMA I/O device using PCI bus and PCI-PCI bridge

A portable computer and corresponding docking station, where the portable computer may be inserted into or removed from the docking station without concern relating to the state of either the portable computer or of the docking station. The hot docking sequence is performed by establishing a direct connection to the primary PCI bus without the risk of any possible system damage, file damage, or data loss. This can be accomplished even while the portable computer system is powered on and is actively running. The present invention prevents glitches from occurring in pre-existing pins and adds four new pins to implement this novel hot docking sequence. Furthermore, hot undocking can be readily performed as well by basically reversing the docking sequence.

Method and system for hot docking a portable computer to a docking

A digital computing system includes a first and second processor clocked for locked step operation. A shared memory stores a linear block codeword across a plurality of byte-wide memory devices. The codeword includes a first dataword and a second dataword. Each of the first and second datawords includes an equal plurality of databits and each includes an equal plurality of checkbits associated therewith. First error detection and correction logic connected to the first processor receives the first dataword and checkbits associated therewith of the codeword addressed by the first processor and a second dataword and checkbits associated therewith of the codeword addressed by the second processor. First error detection and correction logic detects and/or corrects errors in the codeword. Second error detection and correction logic connected to the second processor receives the second dataword and checkbits associated therewith of the codeword addressed by the second processor and the first dataword and checkbits associated therewith of the codeword addressed by the first processor. The second error detection and correction logic detects and/or corrects errors in the codeword.

Error detection and correction for data stored across multiple byte-wide

A computer system includes a central processing unit (CPU), system read-only memory (ROM), a random access memory (RAM) and a system controller. The system ROM includes a reset vector. A portion of the RAM is used to shadow the system ROM. The system controller is connected between the CPU, the system ROM and the RAM. The system memory includes an internal memory for storing first data. The system memory also includes logic which, in response to receiving an access to a reset vector stored in the system ROM, returns the first data stored in the internal memory.

Efficient soft reset in a personal computer

The present invention relates to a system and method for starting and maintaining a Central Processing Unit (CPU) clock even though the CPU clock is operating under a Clock Division Emulation (CDE) scheme. Break Events are broken into different groups with each group of Break Events being mapped to a particular programmable event timer. Each of the programmable event timers have an associated time limit which will keep the CPU clock running for a time commensurate with that group of Break Events. When a Break Event occurs, the programmable event timer associated with that particular Break Event will load the corresponding time limit into the programmable event timer. Once loaded, the programmable event timer will keep the CPU clock running during the entire time limit. Only after all of the programmable event timers have counted down will the CPU clock be allowed to stop.

Growing community of inventors

Phoenix, AZ, United States of America

Gary A Walker