International Business Machines Corporation

Gary A VanHuben

Pak-kin Mak

Michael Andrew Blake

Adrian Eric Seigler

Patrick James Meaney

Carl B Ford, Iii

A method for identifying, managing, and signaling uncorrectable errors among a plurality of clusters of symmetric multiprocessors (SMPs) detects, manages and reports data errors. The method allows merging of newly detected errors, including memory, cache, control, address, and interface errors, into existing error status. Also, error status is distributed in several possible formats, including separate status signals, special UE (uncorrectable errors) ECC codewords, encoded data patterns, parity error injection, and response codepoints. The error status is also available for logging and analysis while the machine is operating, allowing for recovery and component failure isolation as soon as the errors are detected without stopping the machine.

Method for tagging uncorrectable errors for symmetric multiprocessors

A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A receiver receives a plurality of incoming messages via the first or second ring and merges a plurality of incoming message responses with a local outgoing message response to provide a merged response. Each of the plurality of nodes includes any combination of the following: at least one processor, cache memory, a plurality of I/O adapters, and main memory. The system control element includes a plurality of controllers for maintaining coherency in the system.

Coherency management for a 'switchless' distributed shared memory computer system

An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O adapters, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. Local controllers on any given node initiate bus operations on behalf of said processors and I/O adapters on that node. Snoop requests are launched onto the ring topology simultaneously in both directions. As the messages traverse the nodes on the ring, they trigger remote controllers to perform coherent actions such as cache accesses or directory updates. Messages arriving on each node from both directions are combined with each other and with locally generated responses to form cumulative final responses. Additionally, controllers on the requesting node may perform local coherent actions based on the information conveyed by the returning final responses. Overall system coherency is maintained through the use of a dual token based scheme which provide coherency points to permit multiple non-contending requests for the same data unit. The cache coherency methods described herein further ensure the latest copy of data is always accessed or modified even when multiple copies are present throughout the multi-nodal system structure. Traditional cache management states are extended to include Intervention Master and Multiple Copy status which minimize overall bus utilization. A novel ring protocol is contemplated which efficiently packages coherency information into bus operational responses that also allow simultaneous data transfers in the direction of minimal latency.

A system for monitoring hardware events in a computer system implements a hardware event monitor of control registers and has programmable generic fields which can be internally or externally programmed for monitoring events ranging from simple operations to complex event sequences. Using programmed criteria incorporated into the hardware event monitor to events within said computer system are monitored by initiating successive compares of programmed criteria with processing events. The hardware event monitor can trigger external actions upon successful detection of compares indicating that all criteria programmed into the hardware event monitor have been achieved. None of the bits within the Control Registers are mutually exclusive which allows multiple scenarios to be programmed. The hardware event monitor and system trace controls act as a single unified entity with remote programming of said hardware event monitor and trace controls over a UBUS to permit capturing and logging problem debugging and instrumentation data for use in remote system administration, technical support assistance, field and customer engineering applications, and performance analysis, and hardware error injection for recovery and diagnostic testing, and enabling dither to break resource deadlocks.

Programmable hardware event monitoring method

A remote resource management system for managing resources in a symmetrical multiprocessing comprising a plurality of clusters of symmetric multiprocessors having interfaces between cluster nodes of the symmetric multiprocessor system. Each cluster of the system has a local interface and interface controller. There are one or more remote storage controllers each having its local interface controller, and a local-to-remote data bus. The remote resource manager manages the interface between two clusters of symmetric multiprocessors each of which clusters has a plurality of processors, a shared cache memory, a plurality of I/O adapters and a main memory accessible from the cluster. This remote resource manager manages resources with a remote storage controller to distribute work to a remote controller acting as an agent to perform a desired operation without requiring knowledge of a requester who initiated the work request. Said work is transferred only when a remote requester is available for processing of the work, without a need for constant communication between the clusters of symmetric multiprocessors.

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Poughkeepsie, NY, United States of America

Gary A VanHuben