International Business Machines Corporation

Gary A Van Huben

Patrick James Meaney

Steven R Carlough

Susan M Eickhoff

Joseph Lawrence Mueller

Stephen J Powell

Jie Zheng

Warren Edward Maule

John Steven Dodson

Eric Eugene Retter

Stephen P Glancy

David D Cadigan

John Stanley Bialas, Jr

Glenn David Gilda

Scot H Rider

Adrian Eric Seigler

Irving G Baysah

Pak-kin Mak

Michael Andrew Blake

Michael B Spear

Karthick Rajamani

Malcolm Scott Allen-Ware

Gregory Scott Still

Brad William Michael

Todd Jon Rosedahl

Stephen Dale Wyatt

Michael Steven Siegel

William Vincent Huott

Vesselina K Papazova

Kevin M Mcilvain

Lawrence D Curley

David Allan Webber

Steven J Hnatko

James Charles Gregerson

Samir Kirit Patel

Markus Cebulla

Elspeth Anne Huston

Logan I Friedman

Walter Pietschmann

Nicholas Steven Rolfe

Kevin M McIvain

Joyce Chang Mak

Thomas Bernard Warnock

Darryl James McDonald

Kevin Charles Gower

Robert Brett Tremaine

Christopher J Berry

Craig Raymond Walters

Gary E Strait

Michael Joseph Carnevale

Donald J Ziebarth

Edward James Kaminski, Jr

Jonathan Yang Chen

Michael Wayne Harper

Dinesh Kumar

Elianne A Bravo

Jeremy R Neaton

Steven Mark German

Ryan Patrick King

Steve Yun Xiao

Margaret Annabelle Allen

Addison Daniel Ferrari

Edward J Kamindki, Jr

Colleen Ann Weller

According to a technique of code development, a plurality of subsystem power profiles for a corresponding plurality of subsystems of a host platform in a production data processing environment are received. Each of the subsystem power profiles specifies power consumption of a corresponding one of the plurality of subsystems across a range of workload traffic intensities. Based on the plurality of power profiles, source code and/or software architecture of the source code is power-optimized in a development data processing environment such that, in the production data processing environment, power consumption per unit of performance of an executable program derived from the source code is improved.

Cross-layer power optimization of program code and/or software architecture

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.

Host synchronized autonomous data chip address sequencer for a distributed buffer memory system

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

Address/command chip controlled data chip address sequencing for a distributed memory buffer system

Aspects include configuring a plurality of functional self-test controllers in a test control device to run a plurality of functional test cases in parallel on a plurality of devices under test. Test traffic is arbitrated between the functional self-test controllers and a plurality of packeted protocol layer interfaces of the test control device. One or more protocol specific conversions are performed between the test traffic and a device-specific packeted protocol of each of the devices under test. Payload checking is performed between the packeted protocol layer interfaces and the devices under test to verify responses of the devices under test to the functional test cases.

Packeted protocol device test system

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

A calibration controller determines a latest arriving data strobe from at least one data chip at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller determines whether external feedback of the at least one data chip is required. The calibration controller, in response to determining that external feedback of the at least one data chip is required, aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe by applying a 180 degree phase align of the chip clock through one or more latches, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary.

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.

Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection

A calibration controller of a receiving chip learns a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of the receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary. The calibration controller dynamically adjusts a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

Reducing chip latency at a clock boundary by reference clock phase adjustment

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one aspect, the data buffer circuit receives a next to be used store data tag from a Host wherein the store data tag specifies the data buffer location in the data buffer circuit to store data, and in response to receiving store data from the Host, moves the data received at the data buffer circuit into the data buffer pointed to by the previously received store data tag.

Host controlled data chip address sequencing for a distributed memory buffer system

A calibration controller determines a latest arriving data strobe at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary. The calibration controller aligns the chip clock with a high speed clock for controlling an unload pointer to unload the data from the second data buffer to a serializer in the read data path, wherein the data cross a second clock boundary from the second data buffer to the serializer, to minimize a latency in the read data path across a second clock boundary.

A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Scalable data collection for system management

A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.

Register access in a distributed memory buffer system

Growing community of inventors

Poughkeepsie, NY, United States of America

Gary A Van Huben