International Business Machines Corporation

Globalfoundries Inc.

Gary A Tressler

Diyanesh B Chinnakkonda Vidyapoornachary

Andrew Dale Walls

Prasanna Jayaraman

M Dean Sciacca

Janani Swaminathan

Kyu-hyoun Kim

Saravanan Sethuraman

Adam J McPadden

David D Cadigan

Trinadhachari Kosuru

Diyanesh Babu C Vidyapoornachary

William Vincent Huott

Anuwat Saetow

Charalampos Pozidis

Nikolaos Papandreou

Charles John Camp

Thomas P Parnell

David Michael Daly

Dustin J Vanstee

Abhijit Saurabh

Harish Venkataraman

Roman Alexander Pletka

Gregg Steven Lucas

Thomas Mittelholzer

Aaron Daniel Fry

Samuel R Connor

Michael Cracraft

Thomas J Griffin

Lincoln T Simmons

William Hugh Cochran

Franck Excoffier

Vijay Anand Mathiyalagan

Adam C Chunn

Jeffrey P Gambino

Evangelos Stavros Eleftheriou

Timothy J Fisher

Eduard Albert Cartier

Sasa Tomic

Ioannis Koltsidas

Edgar Rolando Cordero

Stephen P Glancy

Diyanesh B Vidyapoornachary

Paul Anthony Zulpa

Joel K Popelsky

Karen J Gilsdorf

Archana Shetty

David R Whalen

A computer-implemented method for command-address-control calibration of a memory device includes starting, via a processor, a controller clock for the memory device, releasing, via the processor, a reset on the memory device, running, via the processor, a calibration pattern for calibrating the memory device by placing the memory device in calibration mode, where the calibration pattern is initiated prior to an initialization of the memory device, calibrating, via the processor, the memory device with a calibration setting based on the calibration pattern, and initializing the memory device based on the calibration setting.

Memory device command-address-control calibration

Embodiments herein describe a memory system that queues program requests to a block of flash memory until a predefined threshold is reached. That is, instead of performing program requests to write data into the block as the requests are received, the memory system queues the requests until the threshold is satisfied. Once the buffer for the block includes the threshold amount of program requests, the memory system performs the stored requests. In one embodiment, the memory system erases all the pages in the block before writing the new data in the program requests into the destination pages. The data that was originally stored in the pages that are not destination pages is rewritten into the pages. In this example, the queued program requests can be written into the pages using one erase and write step rather than individual erase and write steps for each of the requests.

Delay programming requests in flash memory

An apparatus and method may detect and reduce noise on data busses by adjusting the phase of the input/output (I/O) signals in a controlled, predictable manner. The control may allow a maximum data rate to be achieved. In one embodiment, an algorithm used to determine phase change data may be handled by a feedback loop and may be dynamically adjusted. The system may detect noise on rails and critical signals for logging in call home data. The system may maintain a database of settings as a function of a workload. The system may be used in the field as the workload changes to determine that a signal has reached a first threshold. In response to determining that the signal has reached the first threshold, an alert is initiated. A system may determine that the signal has reached a second threshold. In response to determining that the signal has reached the second threshold, the signal may be coupled to logic circuitry.

Mitigation of side effects of simultaneous switching of input/output (I/O data signals

In an example, a method of correcting an error in a memory device includes determining a temperature profile associated with a region of a memory device. The temperature profile is one of a plurality of temperature profiles each associated with a respective region of a plurality of regions of the memory device. The method includes determining a correction capability based on the thermal profile. The method also includes correcting an error in the memory region using the determined correction capability.

Correcting an error in a memory device

Embodiments herein describe a 3D flash memory system that includes multiple blocks where each block contains multiple pages arranged in a vertical stack. Instead of having a single command line indicating whether a read or program is to be performed, separate command lines are coupled to each of the blocks. As a result, if the memory system identifies a read request and a program request to different blocks, the requests can be performed in parallel. In one embodiment, a program command line is used to perform a program request on a first block while a read command line is used to perform a read request on a second block in the 3D flash memory system in parallel. Furthermore, because a program request can take much longer to complete than a read request, the 3D flash memory system can perform multiple read requests in parallel with the program request.

Parallel read and writes in 3D flash memory

A data storage system includes a non-volatile memory array controlled by a controller. In response to receipt of write data to be written to the non-volatile memory array, the controller determines whether a read count of an unfinalized candidate block of storage within the non-volatile memory array satisfies a read count threshold applicable to the block. In response to determining that the read count of the unfinalized candidate block satisfies the read count threshold, the controller finalizing programming of the candidate block and programming an alternative block with the write data.

Reducing read disturb effect on partially programmed blocks of non-volatile memory

An SSD has a plurality of dies, with each die having a storage capacity. The storage capacity of each die is divided into a primary capacity and a spare capacity. A primary die has a maximum primary capacity, and a sum of the spare capacities of the remaining dies is greater than the maximum primary capacity. Data stored on the SSD is distributed among the primary capacities of the dies. When a failure of a first die is detected, data stored on the failed first die is migrated to the spare capacity of at least one of the remaining dies.

Using spare capacity in solid state drives

A solid state disk (SSD) device has a set of data transfer parameters which regulate I/O operations of the SSD device. The temperature of the SSD device is monitored using temperature readings from a temperature sensor. The temperature of the SSD device satisfies a temperature threshold. A data transfer modification is determined. The data transfer modification is capable of modifying one or more data transfer parameters of the set of data transfer parameters. The set of data transfer parameters is modified using the data transfer modification in response to the temperature of the SSD satisfying the temperature threshold. One or more I/O operations are completed with the SSD device using the modified set of data transfer parameters.

Managing temperature of solid state disk devices

An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.

Concurrent upgrade and backup of non-volatile memory

A computer-implemented method for controlling power consumption in a non-volatile dual inline memory module (NVDIMM-N) may include determining, via a processor, whether the NVDIMM-N is receiving power from a main power source, inactivating, via the processor, a data bus connected to an NVDIMM-N memory group responsive to determining that the NVDIMM-N is not receiving power from the main power source, backing up data stored in the NVDIMM-N memory group, via the processor, to a non-volatile memory module integrated with the NVDIMM-N, where an NVDIMM-N controller can access the NVDIMM-N memory group while backing up, and transmitting, via the processor, a low power command to an NVDIMM-N controller to place the NVDIMM-N memory group in a low power mode.

System and method for conserving energy in non-volatile dual inline memory modules

Delaying programming requests in flash memory

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Sandy Hook, CT, United States of America

Gary A Tressler