Apple Inc.

Qlogic Corporation

Gary A Rogan

Sanjeev K Maheshwari

Lizhi Zhong

Wing Liu

Wenbo Liu

Vishal Varma

Jaeduk Han

Sunil Bhosekar

Ming-Shuan Chen

Govind Kizhepat

John E Nolan

Vikram Karvat

An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

Serial data receiver with sampling clock skew compensation

Method and system for establishing asymmetric transfer rates between a first node and a second node communicating with each other via a network link using Ethernet as a network protocol is provided. The method includes determining during a negotiation process that the first node and the second node have compatible asymmetric capability to set a first rate for transmitting information via the network link and a second rate for receiving information via the network link using Ethernet as the network protocol; and establishing the first rate for transmitting information and the second rate for receiving information. Furthermore, the first node includes a first port having a receive segment and a transmit segment. The transmit segment and the receive segment have separate PLL modules such that the transmit segment can transmit data at a first rate and the receive segment can receive data at a second rate via the network link.

Method and system for using asymetric transfer rates in receive and transmit paths of a network

In some embodiments, a system allowing a flexible upgrade of a computer system (e.g. server) to a high-speed network connection comprises base configuration motherboard or network card including a set of low-speed (e.g. 1 Gbps Ethernet) media access controllers (MACs) each connected to a low-speed physical controller (PHY), and a set of high-speed (e.g. 10 Gbps Ethernet) MACs. An expansion card including high-speed PHYs of choice can be connected by an end user to the base configuration motherboard or network card. A flow classifier classifies data sent/received over both high-speed and low-speed ports, and a single driver may control both high- and low-speed ports. One or both of the motherboard and/or expansion card are configured according to a detected type (e.g. physical layer standard, vendor) of expansion card connected to the motherboard and/or type of physical medium connected to the expansion card.

Flexible server network connection upgrade systems and methods

Growing community of inventors

Los Altos, CA, United States of America

Gary A Rogan