Motorola Corporation

Freescale Semiconductor,inc.

Gary A Mussemann

Ravindraraj Ramaraju

Joseph Charles Circello

Prashant U Kenkare

James G Gay

Eric V Fiene

Mihir S Sabnis

A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.

Sequential digital circuitry with test scan

A method and apparatus for placing a data processor (12) into a low-power mode of operation using a system (10). The system (10) has a processor (12). The processor (12) has access to a bus (18). The bus (18) is coupled to a bus controller (14). The processor (12) sends a broadcast cycle out through the bus (18) when the processor (12) desires to enter a low-power mode of operation. The bus controller (14) determines that the broadcast cycle has been sent on the bus (18). The bus controller (14) waits a predetermined amount of time to process the low-power request and grants permission to the processor (12) to enter the low-power mode via the communication of a transmission termination signal. The processor (12) conditionally drives either logic ones or a tri-state value onto the bus (18) depending upon whether or not the processor (12) has been granted ownership of the bus (18).

Method and apparatus for entering a low-power mode and controlling an

In an integrated circuit microprocessor, an M-bit priority encoder circuit indicates the highest priority bit position that is set in a first portion of an N-bit (N generally being greater than M) data word and provides control information regarding the number of bits that are set. If more than one bit is set, the highest priority bit is reset, the first portion is re-analyzed, and highest priority bit information and control information are again provided. If only one bit or no bit is set in the first portion, a second portion is analyzed, and highest priority bit information and control information regarding the second portion is provided. Analysis of the second portion, and of any subsequent portions, continues in similar fashion until no further bit positions are determined to be set in the data word.

Partial-sized priority encoder circuit having look-ahead capability

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Austin, TX, United States of America

Gary A Mussemann