United States of America As Represented by the Administrator of Nasa

Gary A Crum

David J Petrick

Thomas P Flatley

Alessandro D Geist

Cody Brewer

Nicholas Franconi

Christopher Wilson

Manuel Buenfil

Milton C Davis

Robin A Ripley

Daniel C Espinosa

Alessandro Giest

Jeffrey C Hosler

The present invention relates to a single-board processor card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, including: a field-programmable-gate-array (FPGA) which is reconfigurable in flight; wherein a configuration memory of the FPGA can be scrubbed in flight to correct errors or upsets; and a radiation-hardened monitor (RHM) which provides radiation mitigation and system monitoring of the single-board processor card, and which reconfigures said FPGA during flight, scrubs the configuration memory, and monitors a health of the FPGA. The 1U CubeSat payload form-factor multi-purpose architecture includes a backplane having a plurality of slots, one of the plurality of slots which accommodates the single-board processor card, wherein the backplane routes signals to a plurality of standard-sized processor cards, interchangeably disposed in any of the plurality of slots.

Processor card and intelligent multi-purpose system for use with processor card

A single-board computer system radiation hardened for space flight includes a printed circuit board (PCB) having a top side and bottom side; a reconfigurable field programmable gate array (FPGA) processor device a connector disposed on the top side; a plurality of peripheral components mounted on the bottom side, wherein AC coupling capacitors are configured to select routing between the first FPGA and the second FPGA. An expansion card plug attaches to a connector on the bottom of the PCB and a frame is mounted to the PCB.

SpaceCube V3.0 single-board computer

A processing system including an FPGA having a dual port RAM and for use in hostile environments. The FPGA includes three portions: a C&DH portion; a first scratch pad portion receiving a first set of data, processing the first set of data, and outputting a first set of processed data to a first location of the RAM; and a second scratch pad portion receiving a second set of data identical to the first set of data, processing the second set of data in the same way that the first set of data is processed, and outputting a second set of processed data to a second location of the RAM. The C&DH portion compares the first set of processed data to the second set of processed data and, if the first set of processed data is the same as the second set of processed data, outputs one set of processed data.

Radiation-hardened processing system

Growing community of inventors

Silver Spring, MD, United States of America

Gary A Crum