Emc Corporation

Wang Laboratories, Inc.

Gary A Cardone

Jack Justin Stiffler

James M Nolan

Stuart P MacEachern

James A Wentworth

Raju C Bopardikar

Jacob Y Bast

Zdenek Radouch

David E Kaufman

Bruce D McLeod

David J Angel

James P Moskun

Mark D Holbrook

Bruce Patterson

A data system architecture is described that allows multiple processing and storage resources to be connected to multiple clients so as 1) to distribute the clients' workload efficiently across the available resources; and 2) to enable scaleable expansion, both in terms of the number of clients and in the number of resources. The major features of the architecture are separate, modular, client and resource elements that can be added independently, a high-performance cross-bar data switch interconnecting these various elements, separate serial communication paths for controlling the cross-bar switch settings, separate communication paths for passing control information among the various elements and a resource utilization methodology that enables clients to distribute processing or storage tasks across all available resources, thereby eliminating 'hot spots' resulting from uneven utilization of those resources.

Method and apparatus for implementing high-performance, scaleable data processing and storage systems

An information processing system includes a processor responsive to instructions for performing operations. The processor includes instruction queue for fetching and storing instructions in advance of execution and the system is responsive to certain of the instructions for causing execution of a corresponding sequence of instructions. A prefetch monitor includes circuitry for detecting instructions which may result in the execution of a corresponding sequence of instructions. The prefetch monitor further includes an instruction substitution circuit which is responsive to the detecting circuitry for inhibiting the reading of following instructions from a memory to the processor and is responsive to instruction fetching operation of the processor for reading null instructions to the processor. The prefetch monitor also includes a synchronization which is responsive to a fetching operation of the processor circuit for detecting transfer of execution to a next valid instruction, wherein the substitution circuit is responsive to the synchronization circuit for resuming reading of instructions from the memory to the processor with the next valid instruction. The synchronization includes circuitry for maintaining synchronization between the operations of substituting null instructions and the execution of the instructions. In a specific implementation, the instructions which may result in the execution of a corresponding sequence of instructions are foreign to the system, a corresponding non-maskable interrupt results in the execution of a routine which emulates the execution of the foreign instruction and the null instructions are jump-to-self instructions.

Apparatus and method for monitoring and controlling the prefetching of

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Groton, MA, United States of America

Gary A Cardone