National Semiconductor Corporation

Gary A Brown

Jitendra Mohan

John Andrew Campbell

Luan Minh Vu

Neal L Horovitz

Siew Siong Teo

A power management circuit is arranged to apply power to and remove power from its own oscillator to conserve power. A power-on reset circuit provides a power-on-reset signal to a state machine. The state machine contains states that are programmed with information that is used to power up or down various subsystems within a device that includes the power management systems, including the oscillator of the state machine. The state machine assumes a known state and applies power to the oscillator in response to the power-on-reset signal. The state machine changes states in response to system events (e.g., a keypress). The state machine also maintains power to the oscillator during the period of time and which the state machine requires clock signal from the oscillator. The state machine can power down the oscillator to conserve power when the state machine does not require a clock signal from the oscillator.

Power conservation system and method

A polysilicon fuse trim read cell utilizes a fuse structure in a single bit memory cell. When the fuse structure is blown, the memory cell can be read and its stored value retained as a digital output. The cell uses no power in the steady state.

Polyfuse trim read cell

In a line driver that utilizes a digital-to-analog converter (DAC) to generate a current that is used to form an output voltage V,, variations in the output voltage V,are minimized by a calibration circuit that senses the output voltage V,, compares the output voltage V,to a reference voltage, and then increments or decrements the bias current fed into the DAC to match the output voltage V,to the reference voltage.

Calibrated line driver with digital-to-analog converter

A calibration circuit adjusts a differential output voltage from a line driver circuit when the differential output voltage falls outside a specified tolerance range. The calibration circuit includes a sample and hold circuit which samples the differential output voltage and holds a representative signal. A comparator compares the held signal with a reference voltage signal. When the held signal is greater than the reference voltage signal the comparator outputs a LOW signal and when the held signal is less than the reference voltage signal the comparator outputs a HIGH signal. The comparator output signal is stored in a memory circuit of a control logic. The control logic instructs an up/down counter to increment when the comparator output is LOW and to decrement when the comparator output is HIGH. A calibration current source sinks a unit of calibration current when the comparator output is LOW and sources a unit of calibration current when the comparator output is HIGH. The calibration current is added to an input current to calibrate the differential output voltage towards the specified tolerance range. In a next cycle of the calibration sequence, if a new comparator output signal is different from that stored in the memory circuit, the calibration sequence ceases. However, if the new comparator output signal is the same as that stored in the memory circuit the calibration sequence continues.

Line driver calibration circuit

A stacked current mirror circuit includes four N-channel MOS transistors. One transistor serves as an input device for conducting via its drain, a majority of the reference current. Another transistor is connected as a mirroring device, with its drain coupled to a voltage source, its gate coupled to the gate of the input device, and its source coupled to the source of the input device at a first common node. These two transistors couple to form a first current mirror circuit which couples to the input of a second current mirror comprising the third and fourth transistors. The drain and gate of the third transistor couple to the first common node and the gate of the fourth transistor. The sources of both the third and fourth transistors couple to a second common node (e.g., ground), and the drain of the fourth transistor provides the output. As a result, current is mirrored from the input device transistor to the mirroring device transistor, and then forced through the third transistor. The current is then mirrored from the third transistor to the fourth transistor which forces the current to the output line.

Current mirror current source with current shunting circuit

A current mode driver capable of driving both 10 Base-T signalling and 100 Base-T signalling in a Local Area Network (LAN) includes two or four current sources. In a first embodiment, a differential signal generator drives four current sources. The generator outputs four signals, one of which is received by each current source. Using these signals, two of the current sources push or pull current across the load in one direction, while the other two current sources push or pull current across the load in the other direction, such that a full differential signal is generated across the load. In another embodiment, a signal generator drives two current sources which drive into the load one at a time. Two switches provide either high resistance or low resistance during half of a signal cycle such that current is pulled through the load in one direction, and prevented from flowing through the load in the other direction. When one current source turns on upon receipt of an input signal, one switch provides low resistance such that when the current source drives current into the load a voltage is generated across the load. At the same time, the other switch provides high resistance such that virtually no current is conducted. In this manner, only one current source pulls current across the load at a given time, while the other current source remains in a standby state.

Differential current mode driver

An analog-to-digital converter (ADC) voltage offset (VOS) reduction circuit architecture is for use with an ADC that includes a resistive ladder network and a differential-to-single ended converter. The DC level of the single-ended output of the differential-to-single ended converter is nominally set at the mid-point of the resistive ladder network. The VOS reduction circuit includes a VOS comparator bank that receives the single-ended output, compares it with a plurality of input signals from the resistive ladder network, and provides the result of the comparison as a plurality of VOS comparator bank signals. A current digital-to-analog converter (IDAC) is coupled to receive the VOS comparator bank signals, via a latch bank, and to provide a current responsive thereto. The current from the IDAC may be provided as a trim current for adjusting the DC level of the single-ended output of the ADC differential-to-single ended converter to be closer to the mid-point of the resistive ladder network, thus reducing voltage offset caused, for example, by variations in process and temperature.

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Fremont, CA, United States of America

Gary A Brown