Intel Corporation

Gary A Andrew

Efraim Rotem

Doron Rajwan

Avinash N Ananthakrishnan

Ryan Donovan Wells

Tawfik Arabi

Srirama Pedarla

Abderrahim Doukali

Greg Eberlein

Dave Riendeau

Nicholas J Freij

Ryan D Anderson

According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device.

Method, apparatus, and system for energy efficiency and energy conservation by mitigating performance variations between integrated circuit devices

A system for identifying and sorting integrated circuit devices based on an encrypted Fuse ID information such as manufacturing and test information stored in the integrated circuit device, includes a test fixture for receiving an integrated circuit device to be identified and sorted. The system further includes a portable, user friendly processor communicatively coupled to the test fixture to read the stored encrypted device identification data from the integrated circuit device and decrypt the read encrypted Fuse ID information, and to compare the decrypted device identification data to a previously entered sort criteria and to identify and sort the integrated circuit device based on the outcome of the comparison.

Test system for identification and sorting of integrated circuit devices

An apparatus that can determine whether a Tva parameter and a Tvb parameter of a device under test (DUT) complies with a design specification where the device under test is coupled to a secondary device. The Tvb parameter corresponds to a setup time of the secondary device. The Tva parameter corresponds to the hold time of the secondary device. The apparatus allows the DUT to be coupled to a secondary device that normally operates with the DUT. The apparatus writes data to the DUT and secondary device. The data is then written back to the apparatus which then determines whether the DUT complies with the Tvb and Tva design specifications. The apparatus may also implement tunable delay circuits to compensate for different setup and hold times of the secondary device.

Test and characterization of source synchronous AC timing specifications by trace length modulation of accurately controlled interconnect topology of the test unit interface

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El Dorado, CA, United States of America

Gary A Andrew