Honeywell Information Systems Inc.

Motorola Corporation

Garvin Wesley Patterson

Marion G Porter

Earnest M Monahan

William A Shelly

Jaime Calle

John M Woods

Edward F Weller, Iii

Donald V Mills

Nicolas S Lemak

Wolfgang G Stehr

A computer system includes multiple memory arrays, each potentially as large as the maximum number of locations for which the associated processor can generate unique addresses. During the processing of such instructions a memory array selection mechanism permits data to be read from or written into any of the memory arrays. Program control may be transferred from an instruction in one memory array to an instruction in another memory array. In addition, memory references may be made to more than one memory array.

Memory array selection mechanism

A central processing unit wherein instruction fetch and execution is performed by a mechanism featuring an instruction look ahead mechanism whereby fetching and processing of the next software instruction is commenced as a last step of the currently executing software instruction, and the currently executing software instruction is terminated by the first portion of the next software instruction.

Instruction look ahead having prefetch concurrency and pipeline features

An input/output system includes at least a pair of processing units and system interface apparatus for comparing the results produced by both halves of the pair during normal system operation under control of a main or host processing unit. The system interface apparatus includes comparison circuits for detecting a mis-compare between the results of each half and sequence control logic circuits which are conditioned upon the occurrence of a mis-compare to unlock or deconfigure the pair to establish in a predetermined manner which of the processing units is faulty. The system interface apparatus, following signal indications of a certain minimum confidence within a processing unit, continues testing of the processor using stored diagnostic routines to determine which one of the processing units is good. It then stops the operation of the bad processing unit and enables system operation to be continued with the good processing unit. To ensure reliable processing, both halves of the pair are tested when a miscompare cannot be related to an error condition associated with one of the pair notwithstanding the fact that the first processing unit tests well. Following reconfiguration, the operating system associated with the system provides periodic testing of the good processing unit, thereby ensuring that the system continues to operate reliably.

Input/output processing system utilizing locked processors

A dispatcher mechanism for assigning to a processor the highest priority peripheral having the highest priority request. In a data processing system having at least one processor, and a plurality of peripheral devices coupled to a system interface unit SIU utilized for communication between said processor and peripheral devices, and also having a plurality of processes competing for control of said processor, a priority interrupt mechanism determines the highest priority peripheral having the highest priority request and then provides an interrupt signal to the processor. A release instruction REL is used to exit the process. The dispatcher mechanism dispatches data to the processor upon request from the processor in order to give control of the processor to the highest priority request.

Apparatus for dispatching data of the highest priority process having

A firmware/hardware mechanism in a general purpose computer system automatically provides alternate addressing paths for addressing data in the same or another main memory module when a failure is detected in a portion of the main memory or main memory module. Two types of memory failures are detected and an alternate path provided for each type of failure. The first type is a failure in a memory which is not detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an exception processing mechanism to provide an alternate path to a good memory module. The second type of failure is detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an interrupt processing mechanism to provide an alternate path to a good memory module.

Fail soft memory

An input/output data processing system includes a plurality of active modules, a plurality of passive modules and at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. Each module connects to one of the ports by a plurality of different interfaces. The active modules include an input/output processing unit for processing interrupts and executing command sequences and a multiplexer unit for directly controlling transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. Different ones of the modules of the system include the programmable interface used for transferring command information to the multiplexer unit and to the devices associated therewith for enabling a different type of control to proceed in parallel with input/output data transfer operations. Each multiplexer unit includes a plurality of storage registers which are operatively coupled to the programmable interface associated therewith for receiving control information therefrom designating the priority to be given by the unit to the processing of different types of interrupt signals received from devices associated therewith in addition to information designating which one of a set of processing routines to be used in servicing the interrupt.

Programmable interface apparatus and method

A microprogram control system includes first and second control stores. The first is a pathfinder control store which is addressed initially by the operation code of a program instruction for read out of first and second addresses. The first address is used for accessing a standard microinstruction sequence during a first phase of operation. The second address is used for accessing an execution microinstruction sequence during a second phase of operation, both phases being required for executing the operation specified by the operation code of the program instruction. Means coupled to the second control store enable the control store to return to the standard microinstruction sequence following the completion of the second phase of operation when the instruction being executed requires the completion of additional operations before its execution can be terminated.

Pathfinder microprogram control system

Priority interrupt hardware monitors for the existence of, and determines the relative importance of requests to determine or attempt to determine when to interrupt an executing process on a processor. The processor may be interrupted only when the hardware determines that something more important needs to be done than what is being done by the currently executing process. Additionally, the processor may set interrupts for itself so that a portion of an executing process may be executed at a higher priority than that required for the remaining portion of the same process.

Priority interrupt mechanism

An input/output processing system includes a plurality of active modules, a plurality of passive modules, at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. The active modules include an input/output processing unit which processes interrupts and executes command sequences and a multiplexer unit which directly controls transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. The system interface unit which operatively provides connections between the different modules includes apparatus for generating steering codes defining the physical location of each module requiring service by another module of the system. The system interface unit appends information provided by the particular module generating a requesting request for attention to the steering code generated. The generation of steering code information by the system interface unit and the module included in such requests insures that only authorized accesses are made to the different modules during the input/output processing unit's execution of programs during the running of processes associated therewith.

Steering code generating apparatus for use in an input/output processing

An input-output processing system which performs communication and control functions in a larger data processing system includes a processor for address development to paged memory and program instruction execution for I/O command sequences. In generating memory addresses, instructions are provided an address syllable which references a processor register as an index and a displacement. The contents of the register and the displacement define a memory effective address. A scratchpad memory is provided for storing page table words in levels corresponding to priority levels of processes, and stored page table words are accessed according to the least significant bits of the page number of the effective address. A page base address is taken from an accessed page table word and is concatenated with the effective address to define an absolute memory address.

Method of generating addresses to a paged memory

An input-output processing system (IOPS) which performs both the communication and control functions in a large scale data processing system is disclosed. By relieving the main data processor of these functions more efficient use of the entire system is made possible. The IOPS includes a processor to develop addresses for a paged memory and institute execution of input-output command sequences.

Growing community of inventors

Glendale, AZ, United States of America

Garvin Wesley Patterson