Micron Technology Incorporated

Garth N Grubb

Dennis G Montierth

Marco Sforzin

Daniele Balluchi

Giorgio Servalli

Angelo Visconti

Amitava Majumdar

Massimiliano Patriarca

Anthony M Geidl

Shawn M Hilde

Mow Yiak Goh

Wesley W Borie

Senthil Murugan Thangaraj

Miguel Mares

Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.

Memory failure prediction and mitigation

An exemplary memory includes a first sub-wordline (SWL) driver configured to provide first data from a memory cell array, a second SWL driver configured to provide second data from a memory cell array, and an input/output (I/O) circuit configured to receive the first data and the second data from the first and second SWL drivers, respectively. The I/O circuit including a data terminal mapping circuit configured to selectively route the first data and the second data to different respective data terminal based on a data terminal mapping setting.

Apparatuses and methods to perform DQ swapping on memory

Methods, systems, and devices for a self-refresh state with decreased power consumption are described. A memory system may enter a self-refresh state to refresh a set of rows of memory cells at the memory system. Based on entering the self-refresh state, the memory system may execute a first set of refresh operations on the rows of memory cells according to a first rate. Additionally, the memory system may determine, while in the self-refresh state, whether to decrease the rate for executing the refresh operations to a second rate based on whether each of the rows of memory cells is refreshed according to the first rate. In cases that the memory system determines to decrease the rate for executing the refresh operations, the memory system may execute a set of second refresh operations on the rows of memory cells according to the second, slower, rate while in the self-refresh state.

Self-refresh state with decreased power consumption

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Boise, ID, United States of America

Garth N Grubb