Motorola Corporation

Advanced Micro Devices Corporation

Globalfoundries Inc.

Garth D Hillman

Geoffrey S Strongin

Ralf Findeisen

Andrew R Rawson

Gary H Simpson

Sangil Park

David W Smith

Bradley Martin

Charles D Thompson

John E Lane

Dion M Funderburk

Avner Goren

Joseph P Gergen

Clark L Buxton

Robert Victor Holland

Judah L Adelman

Paul Marino

Patrick K Kelly

In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the modification. The circuitry is configured to detect the instruction or its memory operands and cause a transition to Known Good Code (KGC), wherein the KGC is protected from unauthorized modification and is provided from an authenticated entity. The KGC comprises code that, when executed, emulates the modification. In another embodiment, an integrated circuit comprises at least one processor core; at least one other circuit; and a KGC source configured to supply KGC to the processor core for execution. The KGC comprises interface code for the other circuit whereby an application executing on the processor core interfaces to the other circuit through the KGC.

Known good code for on-chip device management

Uses of known good code for implementing processor architectural modifications

A computing device has a plurality of subsystems located in subsections that are moveable with respect to each other. Communication between the subsections is accomplished with wireless transceivers transmitting over the air gap interface separating the subsections. Data from multiple communicating subsystems in the subsections is multiplexed into a single data stream and encoded into the communication protocol of the wireless transceivers. The encoded data stream is transmitted to a compatible transceiver where it is decoded. The decoded data stream is demultiplexed into individual data streams for each of the communicating subsystems. The wireless transceivers include multiple communication protocols and transmission frequencies from radio frequencies to optical frequencies. Optical fibers, transmission lines or waveguides may be used to transmit signals within each subsection depending on the wireless technology and protocol.

Wireless interface

A network includes an Internet connection element and a plurality of wireless device access points. Each of the plurality of wireless device access points includes a wireless transceiver and each of the plurality of wireless device access points is coupled to the Internet connection element. A location of at least one of the plurality of wireless device access points is represented on a map that is accessible via the Internet.

Method and system for locating a wireless network access point at a mobile computing device

A speakerphone system ( ) implements automatic gain control (AGC) when it is in a talk mode. While in the talk mode, the speakerphone system ( ) applies a gain factor determined by conventional AGC techniques. The inverse of this gain factor is applied to the received signal to avoid the need to adapt the coefficients of an echo canceller, such as an acoustic echo canceller (AEC) ( ), as the volume level changes. The speakerphone system ( ) determines whether it is in the talk, double-talk, or listen mode by adaptively changing energy thresholds which define these modes, in dependence on the distribution of ratios of the transmitted energy to received energy. The speakerphone system ( ) also varies a loop gain in dependence on the separation between the distribution of energy ratios in the talk mode and in the receive mode. This automatic loop gain adjustment ensures loop stability.

Method and apparatus for controlling a full-duplex communication system

A data ALU (arithmetic logic unit) (54) in a data processing system (20) performs both 24-bit arithmetic, and 16-bit exact arithmetic (including shifting and logical operations) using the same hardware. For a multiply/accumulate operation in 16-bit exact mode, shifting operations are used to align the operands so that 16-bit exact mode is transparent to a user. An entire instruction set can be executed in 24-bit mode or 16-bit exact mode. The same instructions and hardware are used in both modes. A transition between modes is performed by changing a status bit (97) in a status register (95).

Apparatus and method for performing both 24 bit and 16 bit arithmetic

A direct-path echo cancellation circuit includes a loudspeaker (12), first and second microphones (14, 16), and an in-phase signal cancellation circuit (21, 43). The first and second microphones (14, 16) are positioned adjacent the loudspeaker (12) in order to receive in-phase direct-path echo components (31, 32) of an output signal from the loudspeaker (12). The in-phase signal cancellation circuit (21 or 43) combines the in-phase direct-path echo components of the output signal in order to cancel the direct-path echo components. Direct-path echo cancellation helps to reduce howling and/or oscillation in a full-duplex speakerphone system. Also, direct-path echo cancellation provides more dynamic range to an input signal which is provided to a speakerphone signal processing system (26).

Echo cancellation in a full-duplex speakerphone

A digital receiver, such as 'C-QUAM' receiver (10), has phase error correction. In another form, a software program may be executed by a conventional digital signal processor to also implement phase error correction. A digital input signal is demodulated to form an in-phase and a quadrature component. The in-phase and quadrature components are processed by a digital envelope detector (24) to form a composite signal containing left and right audio channel information. The in-phase component and composite signal are both processed by a reciprocal cosine estimator (28) and a quadrature channel circuit (38) to provide a difference signal also containing left and right audio channel information. The difference signal is input to phase error correction circuitry (16, 22, 26) to estimate a phase error of the digital input signal. The estimated phase error is then used to correct an actual phase error of the digital input signal during demodulation.

Circuit and method for phase error correction in a digital receiver

A filter structure uses multiple discrete filter circuits which are cascaded to provide a multiple tap filter of programmable tap length. In one form, an FIR filter may be implemented wherein each circuit generates partial sum operands which must be added to provide a filter output. The cascaded circuits perform partial addition operations near simultaneously by using a serial addition which is synchronized with a start bit. The number of taps in the filter structure implemented by the cascaded discrete filter circuits is variable and may be programmed with a programmable storage register in each discrete circuit which stores operand data fixing the tap length of each discrete circuit. The multiple filter circuits provide a single filter structure with a large tap length and high sampling rate.

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Austin, TX, United States of America

Garth D Hillman