Cisco Technology, Inc.

Oracle International Corporation

Garry Paul Epps

Michael Laor

Mohammed Ismael Tatar

Eyal Oren

Oded Trainin

Cedrik K Begin

Mark Andrew Gustlin

Earl T Cohen

Promode Nedungadi

Guy Fedorkow

David Belz

Steven Philip Holmes

David Doak

Randall A Johnson

David Delano Ward

Clarence Filsfils

John H W Bettink

Dalit Sagi

John P Prokopik

Michael J Taylor

Christopher Yates Satterlee

Mohammed Tatar

A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network is disclosed. The linecard has two paths: a receive path and a transmit path. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information. Each packet is buffered and enqueued for transmission over the switching fabric to a destination linecard. The transmit path includes a buffer/queuing circuit similar to that used in the receive path. Both enqueuing and dequeuing of packets is accomplished using a CoS-based decision making apparatus.

Pipelined packet switching and queuing architecture

An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets.

A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port. The destination linecard may be the same physical linecard as that receiving the inbound packet or a different physical linecard. The transmit path consists of a buffer/queuing circuit similar to that used in the receive path. Both enqueuing and dequeuing of packets is accomplished using CoS-based decision making apparatus and congestion avoidance and dequeue management hardware. The architecture of the present invention has the advantages of high throughput and the ability to rapidly implement new features and capabilities.

Real-time customer packet traffic is instrumented to determine measured delays between two or more points along a path actually traveled by a packet, such as within or external to one or more packet switching devices. These measurements may include delays within a packet switching device other than the ingress and egress time of a packet. These measured delays can be used to determine whether or not the performance of a packet switching device or network meets desired levels, especially for complying with a Service Level Agreement.

Instrumenting packet flows

An optical packet processor includes one or more optical packet inputs that receive asynchronous optical packets. An optical packet interconnect directs the optical packets from the different optical packet inputs to different optical packet outputs. The optical packets are buffered either before or after being directed from the inputs to the different outputs. Problems associated with optical buffering are overcome by synchronizing the asynchronous optical packets with the optical packet buffers. The novel optical buffer architectures described also reduce or eliminate the use of certain high cost optical components.

Buffering schemes for optical packet processing

Asynchronous optical data is aligned with synchronous convergence points in an optical packet switching system. The convergence points can be any place where data enters an optical packet switching element, buffer stage, switch fabric, etc. The arrival time for data approaching the convergence point is compared with a reference signal associated with the upcoming convergence point. The comparison is used to identify the amount of time-shift required to align the approaching data with the reference signal. Control information is derived according to the comparison and used to control an optical data aligner that synchronizes the data with the convergence point.

Optical data synchronization scheme

An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets. These features can include a recycle path coupling a gather stage circuit and a fetch stage circuit and can include sequence number logic configured to associate sequence numbers with multicast packet headers.

An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports of a network interface. A high priority buffer and a low priority buffer can be assigned to each port of the network interface. The network interface can perform packet prioritization through buffer selection based on priority. High priority packets will be transmitted to an ingress packet processor before low priority packets for a given port.

A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in a multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Using bandwidth management techniques, each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port. The destination linecard may be the same physical linecard as that receiving the inbound packet or a different physical linecard. The transmit path includes a buffer/queuing circuit similar to that used in the receive path and can include another pipelined switch. Both enqueuing and dequeuing of packets is accomplished using CoS-based decision making apparatus, congestion avoidance, and bandwidth management hardware.

High-speed hardware implementation of RED congestion control algorithm

A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.

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Sunnyvale, CA, United States of America

Garry Paul Epps