Credence Systems Corporation

Garry C Gillette

Brian J Arkin

David Scott

David Chan

A parallel processing pattern generation system for an integrated circuit tester includes two pattern memories, a main pattern generator, and two auxiliary pattern generators. Each pattern memory may receive and store data patterns from a host computer before the test. All three pattern generators may produce data pattern sequences in a variety of ways by executing separately stored algorithmic programs. The pattern sequences generated by each of the two auxiliary pattern generators separately address the two pattern memories so that either one or both of the two pattern memories may read out pattern data during a test. The main pattern generator includes a routing circuit for receiving as inputs a portion of the pattern data generated by the main pattern generator itself and the pattern data read out of the two pattern memories. The routing circuit, controlled by another portion of the pattern data produced by the main pattern generator, selects from among its inputs on a bit-by-bit, cycle-by-cycle basis to provide pattern data for controlling tester activities during each cycle of a test.

Parallel processing pattern generation system for an integrated circuit

A current sense circuit for use in a semiconductor tester has a voltage source for forcing a voltage to a first node of the current sense circuit, a current sense resistor having a first terminal connected to the first node and a second terminal connected to a second node for connection to a pin of a device under test (DUT), and a differential amplifier for measuring voltage drop across the current sense resistor. The current sense resistor is composed of a network of switchable semiconductor resistor devices each having at least a first resistance state and a second resistance state, in which the resistor device has first and second different resistance values respectively, and a device for selectively controlling the states of the resistor devices, whereby the resistance value of the current sense resistor can be selectively varied.

Current sense circuit

A modular integrated circuit tester includes a set of tester modules for carrying out a sequence of tests on an integrated circuit device under test (DUT). Each module includes a memory for storing instruction sets indicating how the module is to be configured for each test of the sequence. Before the start of each test, a microcontroller in each module executes an instruction set to appropriately configure the module for the test. The microcontroller in each module thereafter sends a ready signal to a start logic circuit in each other module indicating that it is ready to perform the test. When the microcontrollers of all modules taking part in the test have signaled they are ready, the start logic circuit in each module signals its microcontroller to begin the test. The modules then carry out the test with their activities synchronized to a master clock signal. The process of configuring the modules, generating the ready signals and commencing a test is repeated for each test of the sequence.

Modular integrated circuit tester with distributed synchronization and

A circuit arrangement for use in a semiconductor integrated circuit tester for measuring leakage current supplied from a pin of a semiconductor integrated circuit device under test (DUT) to a programmed voltage level includes a voltage source having an output terminal, a feedback mechanism connected between the DUT pin and the voltage source for controlling the voltage source to force the DUT pin to the programmed voltage level, a capacitor connected between the output terminal of the voltage source and the DUT pin, and a circuit for measuring voltage developed across the capacitor.

Circuit arrangement for measuring leakage current utilizing a

A loading device for use in a tester for testing a semiconductor integrated circuit device (DUT) includes a programmable voltage source for providing a selected voltage at an output terminal thereof and multiple resistive elements each having at least a first state, in which the resistive element is conductive, and a second state, in which the resistive element is substantially non-conductive. The resistive elements are connected as a two-terminal network between the output terminal of the programmable voltage source and a tester pin for connection to a pin of the DUT. A selection device selects the state of each resistive element, whereby the resistance between the output terminal of the programmable voltage source and the tester pin can be selectively varied.

Switchable load for testing a semiconductor integrated circuit device

A delay compensation circuit responds to a sensed change in operating temperature of a CMOS integrated circuit (IC) by appropriately adjusting the IC's power supply voltage so as to prevent the temperature change from affecting IC signal path delays. The delay compensation circuit senses the temperature change by monitoring a temperature sensitive voltage across a diode included in the IC and generates the power supply voltage as an appropriately adjusted linear function of the diode voltage.

System for compensating for temperature induced delay variation in an

A drive arrangement for a semiconductor integrated circuit tester having a tester pin connected by a transmission line to a terminal for engaging a pin of a semiconductor device under test (DUT) includes a driver having an output terminal which can be driven selectively to at least two voltage levels in response to a timing signal and multiple semiconductor resistive elements each having at least a first state, in which the resistive element is conductive, and a second state, in which the resistive element is substantially non-conductive. The resistive elements are connected as a two-terminal network between the output terminal of the driver and the tester pin. By selective control, the resistive elements can backmatch the characteristic impedance of the transmission line.

Backmatch resistor structure for an integrated circuit tester

A load circuit for an integrated circuit tester provides an adjustable load at a terminal of an integrated circuit device under test (DUT) when the DUT is generating an output signal at the terminal. The load circuit includes positive and negative current sources for producing positive and negative currents of magnitudes that are non-linear functions input reference voltages. A diode quad connects the negative current source to the DUT terminal when the DUT output signal is below an input threshold voltage and connects the positive current source to the DUT terminal when the DUT output signal is above the threshold voltage. The current sources provide a non-linear, exponential, transfer function between input reference voltage and output current magnitude so that the current sources provide a relatively wide output current range in response to a relatively narrow input reference voltage range.

Load circuit for integrated circuit tester

A programmable voltage source produces a set of output reference voltages having levels determined by a sequence of input data values, each input data value corresponding to a separate one of the reference voltages. The voltage source includes a charging current generator for generating a charging current and a set of sample and hold circuits, each corresponding to a separate one of the data values, each for producing a separate one of the output reference voltages. The charging current generator receives each data value in succession and supplies a charging current to the corresponding sample and hold circuit and that sample and hold circuit adjusts its output reference voltage by integrating the charging current. The charging current generator monitors the output reference voltage produced by that sample and hold circuit and sets the charging current to a level proportional to a difference between the reference voltage level and a level indicated by the input data. The reference voltage output of the sample and hold circuit therefore stabilizes at the level indicated by the input data.

Growing community of inventors

San Jose, CA, United States of America

Garry C Gillette