International Business Machines Corporation

Kabushiki Kaisha Toshiba

Garrett Stephen Koch

Luigi Ternullo, Jr

John P Connor

Robert Dean Adams

Kevin A Batson

Osamu Takahashi

Erik L Hedberg

Robert E Busch

Orest Bula

Reid A Wistort

Roy Childs Flaker

James J Covino

Alan L Roberts

Steven Ross Ferguson

Jose Roriz Sousa

Michael Brian White

Richard S Gomez

Justin A Woyke

Sebastian Theodore Ventrone

Michael Richard Ouellette

Anthony Gus Aipperspach

Steven Lee Gregor

R Dean Adams

Fred John Towler

Louis Bernard Bushard

Thomas J Eckenrode

Stuart D Rapoport

Akihiko Fukui

A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.

Multiple uses for BIST test latches

A method is provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.

In a first aspect, a first method is provided that includes the steps of (1) transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path; (2) transmitting a second signal, synchronized with the first signal, from the test circuit to the memory via a second signal path; and (3) initiating the test operation on the memory in response to the second signal arriving at the memory. Numerous other aspects are provided.

Methods and apparatus for testing a memory

An integrated circuit including: a set of bitlines; a set of data lines; means for coupling each respective data line to a first respective bitline or to a second respective bitline based on a steering signal, the second respective bitline being adjacent to the first respective bitline; and means for maintaining the first respective bitline at a desired potential after the data line is coupled to the second bitline.

Memory device with data line steering and bitline redundancy

A system and methodology for testing memory in an integrated circuit implementing BIST testing to calculate row and column redundancy and enable replacement of a defective row or column of memory cells. The system comprises circuitry for detecting a first single memory cell failure in a row; and, recording the I/O value of the first Single Cell Fail (SCF). A circuit is provided for detecting whether more than one single cell failure has occurred for a tested row, and, in response to detecting a second SCF, comparing recorded I/O value of the subsequent tested row, with the I/O value associated with the first failed memory cell. Upon detection of defective bits, the defective column and row of memory having corresponding defective bits set is replaced.

Two-dimensional redundancy calculation

A Dynamic Content Addressable Memory (DCAM) cell topology that contains fewer that can perform a &ldquo;hidden&rdquo; refresh of stored data that does not delay nor interrupt the CAM search cycle, thereby providing SCAM-like performance. A non-destructive read operation, is performed such that the stored-data does not have to be written back because of a refresh-read operation. A reliable CAM search can be performed after a read operation and before or even while the refresh-data is being written back. Soft-error detection processes can be performed on each CAM entry during the pendency of the refresh cycle. The DCAM cell can be used in a digital system such as a digital computer and a Network Router.

Dram CAM cell with hidden refresh

A multi-port memory is provided that includes means for receiving synchronous memory requests, means for receiving asynchronous memory requests, and means for processing the received synchronous and asynchronous memory requests simultaneously. Systems and methods that employ the multi-port memory are also provided.

Multi-ported memory with asynchronous and synchronous protocol

A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of faulty cells in each of the columns, storing the column addresses having the given number of faulty cells in first registers, further testing the array along the columns or rows to identify any additional faulty cells while masking the cells having the stored column addresses and storing the row addresses having the faulty cell in second registers until all of the second registers store row addresses, and after all of the second registers store row addresses, continue testing the array while masking the cells having the stored column or row addresses and storing the column addresses of any remaining additional faulty cell in any unused register of the first registers.

Method and apparatus for real time two dimensional redundancy allocation

An Array Built-In Self Test (ABIST) circuit places on-chip circuits such as memory arrays in a known state, then stops. In the alternative, the ABIST circuit may initialize to a particular subcycle within a pattern sequence, and repeatedly loop on the subcycle, or repeatedly loop on the entire pattern sequence.

Enhanced built-in self-test circuit and method

A memory Array Built-In Self-Test (ABIST) circuit is disclosed that will test a multi-port memory array. A programmable pattern generator for the ABIST circuit allows for different R/W data operations to be performed at the same or adjacent address locations within a multi-port memory array. The programmable pattern generator comprises a data generator, a read/write controller, and an address counter, each having the same number of outputs as ports of the multi-port memory array. The programmable pattern generator also comprises a frequency controller. The data generator is programmed with the appropriate data patterns for the memory array, and the read/write controller is programmed with the appropriate read/write patterns for the memory array. The address counter is to provide the same or different addresses on each port of the multi-port array, and the frequency controller is programmed with the appropriate frequency information to determine the number of read/write operations per cell in the memory array. The combination of programmable data, programmable read/write sequences, programmable address counter, and programmable frequency allows for determistic testing of a multi-port memory array, a plurality of single-port memory arrays, or a combination thereof by providing unique read/write sequences to the same or to adjacent memory locations.

Memory array built-in self test circuit for testing multi-port memory

An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC3 subcycle, and an RC4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle. In X4 mode, four memory cycles are performed on each cell, and in X8 mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.

Memory array built-in self-test circuit having a programmable pattern

The present invention provides a device for testing memory having write cycles and read cycles. A BIST state machine changes the data applied to the memory's DI port during read cycles to a value different from that of the data stored in the currently addressed memory location. The BIST-generated expect data also is at a different value from that of data at the memory's DI port and at the same value as the data stored at the current memory address location during read operations. With this arrangement, flush through defects can be detected which would not have been detectable by prior BIST machines.

Test converage of embedded memories on semiconductor substrates

An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC.sub.3 subcycle, and an RC.sub.4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle, In X4 mode, four memory cycles are performed on each cell, and in Xg mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.

A method and circuit are provided to detect if any bit stored in a given location in a memory is different from the data expected. The circuit includes logic to read each of the bits stored in the cells at given locations from memory and to generate a fail signal based on the data expected to be stored if the stored data is different from the expected data. The circuit also preferably includes logic to compare the True data and expect data read from each cell and generating the fail signal if they are the same. Additional logic circuitry is also preferably provided which determines if a node of the circuit remains in a precharged condition.

Growing community of inventors

Cambridge, VT, United States of America

Garrett Stephen Koch