Northrop Grumman Systems Corporation

Garrett A Storaska

Robert Samuel Howell

Harvey C Nathanson

Francis W Hopwood

Christopher F Kirby

Ragini Saxena

Joseph Terence Smith

John B Goodell

Stephen D Vancampen

Novel applications of nanocoil technology and novel methods of fabricating nanocoils for use in such applications and others. Such applications include microscopic electro-mechanical systems (MEMS) devices including nanocoil mirrors, nanocoil actuators and nanocoil antenna arrays. Inductors or traveling wave tubes fabricated from nanocoils are also included. A method for fabricating nanocoils with a desired pitch includes determining a desired pitch for fabricated nanocoil, selecting coiling arm orientation in which coiling arm orientation is arm angle between coiling arm an crystalline orientation of underlying substrate, whereby coiling arm orientation affects pitch of fabricated nanocoil, patterning coiling arm structure with selected coiling arm orientation, and, releasing coiling arm, whereby fabricated nanocoil is formed.

System for fabricating nanocoils using a wet etch technique

A device includes a coiling layer, a circuit device layer and active microelectronic circuitry fabricated on the circuit device layer. The coiling layer is formed onto a surface of and coupled to the circuit device layer. The coiling layer having intrinsic stresses which cause coiling of the coiling layer and the circuit device layer including the microelectronic circuitry as the circuit device layer is released from an underlying substrate. A coiled circuit device is formed.

Coiled circuit device with active circuitry and methods for making the same

A curled transistor comprises a coiled semiconductor substrate having a plurality of concentrically curled layers. Source and drain regions are configured on a portion of the coiled semiconductor substrate, and a gate dielectric is positioned between the source and drain regions. A first set of metallic contacts electrically couple to the source region on the coiled semiconductor substrate and a second set of metallic contacts electrically couple to the drain region on the coiled semiconductor substrate.

Curled semiconductor transistor

Novel applications of nanocoil technology and novel methods of fabricating nanocoils for use in such applications and others. Such applications include inductors or traveling wave tubes fabricated from spiral nanocoils. Such applications includes inductors or traveling wave tubes fabricated from a method for fabricating nanocoils with a desired pitch. Such a method includes determining a desired pitch for fabricated nanocoil, selecting coiling arm orientation in which coiling arm orientation is arm angle between coiling arm an crystalline orientation of underlying substrate, whereby coiling arm orientation affects pitch of fabricated nanocoil, patterning coiling arm structure with selected coiling arm orientation, and, releasing coiling arm, whereby fabricated nanocoil is formed.

Inductors fabricated from spiral nanocoils and fabricated using noncoil spiral pitch control techniques

Improved nanocoils, systems and methods for fabricating nanocoils. Embodiments enable wet etching techniques for releasing coiling arm structures and forming nanocoils. A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer in which SOI wafer includes a buried oxide layer, patterning one or more devices onto a silicon device layer on top of the buried oxide layer, depositing a tensile stressed layer on the silicon device layer so that stressed layer and silicon device layer form a stressed coiling bi-layer, patterning a coiling arm structure on the stressed coiling bi-layer, depositing a metal encapsulation layer on the stressed coiling bi-layer, and releasing the coiling arm structure so that coiling arm coils to form nanocoil. A system for fabricating nanocoils includes a substrate, a coiling arm structure including, a buried oxide layer deposited on the substrate, a stressed coiling bi-layer attached to the buried oxide layer including a silicon device layer that includes one or more devices defined thereon and a stressed nitride layer that provides a tensile coiling stress, and a metal encapsulation layer that protects stressed nitride layer from hydrofluoric (HF) acid used to release the coiling arm structure from the substrate during the wet etch technique so that coiling arm structure coils into nanocoil when released. Improved nanocoils may be fabricated according to these and other methods and systems.

Methods for fabricating nanocoils

A method for fabricating nanocoils and improved nanocoils fabricated therefrom. Embodiments of the method utilizing deep reactive ion etching (DRIE). A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer, in which SOI wafer includes buried oxide layer, patterning one or more devices into a layer of silicon on top of the buried oxide layer, depositing tensile stressed nitride layer on the top silicon layer, patterning coiling arm structure on top silicon layer, patterning an overlapping etch window mask on bottom side of SOI wafer using, in which patterning overlapping etch window mask removes SOI wafer and exposes buried oxide layer in width greater than coiling arm structure, and releasing coiling arm structure so that coiling arm coils to form nanocoil. In embodiments, DRIE is utilized to pattern the overlapping etch window mask.

Method for fabricating nanocoils

A coiled circuit device is produced by forming a circuit layer on a substrate. Optional insulator layers may be disposed above and below the circuit layer. The circuit layer, which may be memory, control, or other circuitry, is released from the substrate such that it coils into a dense, coiled device. A stressed coiling layer may be included which effects coiling when the circuit layer is released.

Coiled circuit device and method of making the same

A small portable 'pocket pen size' projector/image grabber device for allowing an individual to gather, share and exploit information in a projected format in real time, day or night, with other individuals on demand. An ultra high density MEMS mirror display array provides a 1024&#xd7;768 line projection display. An on-axis 512&#xd7;384 color CCD imager is also included resulting in a digitally-aligned image capture and overlay display capability. A sequentially-addressed three color chip laser and low cost plastic optics provides full color high resolution bright displays for group viewing. 3-D color imaging is also provided by a binocular attachment to the device which permits the capturing of three-dimensional imagery.

Pocket-pen ultra-high resolution MEMS projection display in combination with on-axis CCD image capture system including means for permitting 3-D imaging

A micro-electrical mechanical system (MEMS) mirror assembly including an array of micro-mirrors formed on a substrate and having springs on one side and which angularly tilt between ON and OFF states in response to an electrostatic force generated by a voltage applied to an electrode located on the substrate. At least one, but preferably two springs in the form of two thin strips of metal attach to post(s) at the side edge of the mirror and act as springs which provide a restoring force when the mirror is tilted between an OFF state which occurs when the mirror is flat relative to the substrate with no voltage applied, and in the ON state when the mirror is tilted when a voltage is applied.

Growing community of inventors

Reston, VA, United States of America

Garrett A Storaska