Sperry Corporation

Sperry Rand Corporation

Garold S Tjaden

Barry R Borgerson

Merlin L Hanson

Decision and control logic for use in digital computers that operate in cycles provides binary valued decision signals for effecting decisional control within the computer such as that utilized in conditional branching. The decision signals are provided in accordance with binary valued control functions of binary valued static and dynamic control variables utilized in the computer. The dynamic control variables are available in a computer cycle subsequent to the availability of the static variables and represent conditions of various components of the computer. Truth tables of the control functions are stored in logic function memories addressed by logic function selection control fields of computer control words, the control fields selectively addressing the truth tables in accordance with the desired functions. The static variables are utilized for addressing the logic function memories for providing the truth table entries corresponding to the selected function of the static control variables and the dynamic variables select among the addressed truth table entries to provide the binary valued decision control signals. Preferably the logic function memories are implemented by LSI integrated circuits.

Table driven decision and control logic for digital computers

A computer which is configured to perform its operations in overlapped fashion. During each computer cycle the next instruction is fetched, the function designated by the previous instruction is executed, and values are stored that were computed with respect to the instruction previous to the one being executed. Thus a three-way overlap is effected. To minimize time penalties due to conditional branches and jumps, each instruction word includes two next instruction address fields, two function fields and two deferred action fields. The computer includes decision logic for providing binary decision signals for conditionally selecting one of the fields from each of the next address fields, the function fields and the deferred action fields thereby conditionally fetching the next instruction, conditionally selecting the function to be performed and conditionally storing values during the same cycle in accordance with the decision signals. Thus the computer has the capability of performing conditional branches each cycle, in an unbroken rhythm.

Digital computer with overlapped operation utilizing conditional control

A microprogrammable CPU for a computer utilizes an architecture wherein macro instructions of the computer repertoire are executed by micro instruction routines stored in a control store memory. The micro instruction routines are comprised of micro instruction words for controlling the micro operations to be performed in executing the macro instructions. The CPU includes a plurality of local processors each configured to perform a plurality of the micro operations. A macro instruction fetched into the macro instruction register of the computer addresses the corresponding micro instruction routine in the control store memory and the plurality of local processors operate concurrently to simultaneously perform the micro instructions of the routine on behalf of the fetched macro instruction. Thus a stream of macro instructions flowing through the macro instruction register is decomposed into a plurality of concurrently executed micro instruction streams flowing through the respective local processors. Preferably the local processors are constructed utilizing micro processor LSI integrated circuits. Each local processor is operated in an overlapped mode with respect to micro instruction fetching, execution and storage of results. Each local processor has real and phantom branching capabilities provided by plural next address fields and plural function control fields in the micro instruction words. Decision points provided in the computer select between the next address fields and select between the function control fields to perform the real and phantom branching respectively. The decision points are provided by control logic driven by tables storing functions of plural variables where functions and variables are selectable by the micro instruction words.

Microprogrammable computer utilizing concurrently operating processors

The one's complement subtractive arithmetic unit comprises a parallel adder with a connection for providing an end-around carry, from the carry output of the most significant stage to the carry input of the least significant stage. The parallel adder is implemented utilizing multiple bit LSI ALU chips or microprocessor slices that provide group propagate and generate indication signals. Carry look-ahead chips responsive to the group propagate and generate indication signals provide a fast carry arrangement for the arithmetic unit. Circuitry is included to detect when all of the carry propagate indicators are on for providing a signal to the carry input of the parallel adder resulting in the equivalent performance of a one's complement subtractive arithmetic unit.

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Doylestown, PA, United States of America

Garold S Tjaden