Micron Technology Incorporated

Globalfoundries Inc.

Lockheed Martin Corporation

Round Rock Research, LLC

Other

Globalfoundries U.S. Inc.

Nantero, Inc.

Garo Jacques Derderian

Gurtej S Sandhu

Cem Basceri

Vishnu Kumar Agarwal

Demetrius Sarigiannis

Shuang Meng

F Daniel Gealy

Chris M Carlson

Chris W Hill

Donald L Westmoreland

Hui Zang

Mark R Visokay

Jonathan Wesley Ward

Jiehui Shu

Ruilong Xie

Kyle K Kirby

H Montgomery Manning

Ross S Dando

Craig M Carpenter

Allen P Mardian

Min-Hwa Chi

Laertis Economikos

Jinping Liu

Weimin Li

Shesh Mani Pandey

Sam Yang

John M Drynan

Gordon Morrison

Durai Vishak Nirmal Ramaswamy

Eugene P Marsh

Brian A Vaartstra

Huang Liu

Kevin J Torek

Stefan Uhlenbrock

Kevin R Shea

Dan Gealy

Danny Dynka

Huy Cao

Christopher W Hill

Songkram Srivathanakul

Paul Castrovillo

Kimberly R Tschepen

Wen Pin Peng

Adrian N Robinson

Boaz Alperson

Paul J Castovillo

Claude Louis Bertin

John H Zhang

Guy T Blalock

Thomas Rueckes

Terry L Gilton

Michael P Violette

Haiting Wang

Haigou Huang

Todd R Abbott

Daniel J Jaeger

Scott Beasor

Guowei Xu

Suraj Kumar Patil

Chun Yu Wong

Haifeng Sheng

Wen-Pin Peng

Michael J O'Connor

Yurong Wen

J M Drynan

M R Visokay

Paul J Castrovillo

An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.

Vertical resistor adjacent inactive gate over trench isolation

Device structures and fabrication methods for a field-effect transistor. A semiconductor fin includes a first section and a second section in a lengthwise arrangement, a first gate structure overlapping the first section of the semiconductor fin, and a second gate structure overlapping the second section of the semiconductor fin. A pillar is arranged in the first section of the semiconductor fin. The pillar extends through a height of the semiconductor fin and across a width of the semiconductor fin.

Tapered fin-type field-effect transistors

The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.

Hybrid fin cut with improved fin profiles

A resistor for an integrated circuit (IC), an IC and a related method are disclosed. The resistor may include a metal alloy resistor body positioned within a single diffusion break (SDB). The SDB provides an isolation region in a semiconductor fin between a pair of fin-type field effect transistors (finFETs). The resistor in the SDB allows for the resistor to be built at front-end-of-line (FEOL) layers, which saves on space and expense, and allows for precise dimensions for the resistor.

Resistor within single diffusion break, and related method

First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.

Transistor fins with different thickness gate dielectric

At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.

Methods, apparatus, and system for a semiconductor device comprising gates with short heights

The disclosure is directed to methods for forming a set of fins from a substrate. One embodiment of the disclosure includes: providing a stack over the substrate, the stack including a first oxide over the substrate, a first nitride over the pad oxide, a second oxide over the first nitride, and a first hardmask over the second oxide; patterning the first hard mask to form a first set of hardmask fins over the second oxide; oxidizing the first set of hardmask fins to convert the first set of hardmask fins into a set of oxide fins; using the set of oxide fins as a mask, etching the second oxide and the first nitride to expose portions of the first oxide thereunder such that remaining portions of the second oxide and the first nitride remain disposed beneath the set of oxide fins thereby defining a set of mask stacks; and using the set of mask stacks as a mask, etching the exposed portions of the first oxide and the substrate thereby forming the set of fins from the substrate.

Methods for forming fins

Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.

Devices and methods of forming SADP on SRAM and SAQP on logic

One illustrative method disclosed herein includes, among other things, forming an original fin-formation etch mask comprised of a plurality of original line-type features and removing at least a portion of at least one of the plurality of original line-type features so as to thereby define a modified fin-formation etch mask comprising the remaining portions of the plurality of original line-type features. The method also includes forming a conformal layer of material on the remaining portions of the plurality of original line-type features of the modified fin-formation etch mask and performing at least one etching process to remove at least portions of the conformal layer of material and to define a plurality of fin-formation trenches so as to thereby initially define a plurality of fins in the substrate.

Fin cutting process for manufacturing FinFET semiconductor devices

Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.

Methods of forming CMOS based integrated circuit products using disposable spacers

A method of forming a metalized contact in MOL is provided. Embodiments include forming a TT through an ILD down to a S/D region; forming a SiOC, SiCN, or SiON layer on side surfaces of the TT; performing a GCIB vertical etching at a 0&#xb0; angle; implanting Si into the TT by an angled PAI; removing a portion of the TT by Ar sputtering and a remote plasma assisted dry etch process; forming NiSi on the S/D region at the bottom of the TT; and filling the TT with contact metal over the NiSi.

MOL contact metallization scheme for improved yield and device reliability

One method disclosed herein includes, among other things, forming a first spacer proximate gate structures of first and second transistors that are opposite type transistors, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, performing a timed, wet etching process on both of the transistors so as to completely remove the layer of second spacer material from the second transistor while leaving a reduced thickness second spacer positioned adjacent the first spacer of the first transistor, wherein the reduced thickness second spacer has a thickness that is less than an initial thickness of the initial second spacer, and forming a third spacer on and in contact with the first spacer of the second transistor.

Methods of forming reduced thickness spacers in CMOS based integrated circuit products

Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material having a set carbon content conformally within the at least one contact opening disposed over the semiconductor substrate.

Formation of carbon-rich contact liner material

A three-dimensional (3-D) memory stack and a method of formation thereof are described. The 3-D memory stack includes a number of vertically stacked memory devices. Each memory device includes one or more memory cells. Each of the memory cells can be formed on a conductive material. Each memory device further includes one or more selector elements each configured to couple a memory cell of the one or more memory cells to a respective bit line. None of the selector elements is configured as a diode or a transistor element.

High density stacked CNT memory cube arrays with memory selectors

Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material including a carbon-containing species and an elemental carbon disposed therein, the carbon-containing species and the elemental carbon together defining a set carbon content within the carbon-rich contact liner material; and depositing the carbon-rich contact liner material conformally within the at least one contact opening disposed over the semiconductor substrate.

Growing community of inventors

Boise, ID, United States of America

Garo Jacques Derderian