Northern Telecom Limited

Nortel Networks Corporation

Garnet Frederick Gibson

Kenneth James Schultz

Steven William Wood

Farhad Shafai

Robert G Gibbins

Armin George Bluschke

A system includes a plurality of content addressable memory (CAM) arrays and a plurality of logic circuits. The logic circuits are connected to a commonly shared bus. Each of the logic circuits is associated with the respective CAM array. Each of the CAM arrays provides search results (hit, match address and multiple match) in a search operation in response to a clock signal. The hit signals provided from the CAM arrays to the respective logic circuits. Each logic circuit provides an OR logic output signal from a hit signal input from an upstream logic circuit and the hit signal provided by the CAM array associated with that logic circuit, in response to a self-timed signal which is delayed in time from the clock signal. The OR logic output signal provided by the logic circuit is provided to a downstream logic circuit. Thus, the furthest downstream logic circuit provides a hit result of the system in a search operation.

Content addressable memory system with self-timed signals and cascaded

A large-capacity CAM (content addressable memory) is disclosed. RAM core cells are used to store the CAM data. The comparison function is not performed in the core cells, but rather in comparators which are placed adjacent to a plurality of core cells, in such a way that the plurality of core cells shares access to a single comparator. Access to the comparator is shared by a time-division multiplexed means, requiring a plurality of serialized operations. These operations are self-timed and transparent to the user, because they occur in a single cycle of the externally-supplied clock.

Large-capacity content addressable memory

A content addressable memory employs a word-sliced architecture, in order to localize word match logic, and a global data bus, to convey data between the memory input/output circuitry and the plurality of word slices. Timing information is embedded in the global data bus in the form of a model global data signal. This signal interacts with two major control signals to self-time the memory. The number of major control signals is such that all possible memory states are uniquely represented, but the memory cannot power-up in an invalid or unrecoverable state. Three model timing paths are used to match the delay of the self-timing loop with that of the actual operation: one each for READ, WRITE and SEARCH.

Content addressable memory

A multi-port RAM (random access memory) includes RAM cells which are coupled to respective row and column lines of each port. RAM cells selected by signals on the row and column lines of a port store binary data. A ground level voltage is applied onto selected column lines in a shadow write mode. Any short between the active column lines and the column lines in shadow write will result in a significant error voltage being applied to the active column line and invalid read will result. Shorts between column lines from different ports are sensitized.

Multi-port RAM with shadow write test enhancement

Disclosed is an architecture of a RAM (random access memory) with BIST (built-in self test) or functional test function. The RAM has a memory cell for storing differential or single-ended binary data and bit line signals are fully differential or single-ended. Shadow write is applied to read only and read-write bit lines. With the test function, port-to-port bit line shorts and port-to-port word line shorts are sensitized.

Multi-port random access memory with shadow write test mode

The implementation of two-dimensional decoding, necessary to achieve a reasonable array aspect ratio for a large content addressable memory, is achieved by having multiple match lines per physical row, these match lines being physically routed on top of the array core cell in an upper metal layer. To limit power dissipation in the resulting large-capacity content addressable memory, the match function is implemented by two or more NAND chains per word. Means for achieving the precharging and evaluation of these chains, and for implementing dummy chains for the provision of timing information, are also disclosed.

Multi-port random access memory

Disclosed is a design detail for an innovative time multiplexed read port architecture implemented as part of a high-speed 9-port time slot interchange random access memory. It provides a practical, high-speed, low-power and area efficient read port structure to allow eight random access reads per clock cycle. Because all timing is internally generated from a single rising clock transition of a system clock signal, no special control or clocking is required externally to the memory.

A multi-port SRAM (static random access memory) core array has a core cell with a single-ended, pseudo-differential write access port and differential, indirect access read ports. The architecture of the features of the multi-port SRAM core array allows direct scaling of the number of write and read access ports to any practical limit with no adverse effects on cell stability margins and therefore data integrity.

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Nepean, Canada

Garnet Frederick Gibson