3com Corporation

Ross Video Limited

Utah Scientific, Inc.

Garn H Morrell

Gerald A Wilson

Shayne Messerly

David Moore

Spiro Poulis

Harrison Killian

Brady V Brown

Jeff Allen Harrell

David Austin Tubbs

Roger Thornblad

Brent C Higbee

Tom Harmon

Jeff Levie

Reduced-bandwidth versions of display signals that are currently being provided as outputs by multiple computer systems are received and processed for output, at another computer system, of a representation of each of the display signals. The received reduced-bandwidth versions may include, for example, versions of display signals that are generated by applying any one or more of the following to each of the display signals: scaling, segmenting, and compression. At a transmit side, respective requests for different reduced-bandwidth versions of a display signal that is currently being provided as an output by a computer system are received from multiple other computer systems. The different reduced-bandwidth versions of the display signal are generated and transmitted to the requesting computer systems responsive to the requests.

Systems and methods for bandwidth reduction in video signal transmission

Disclosed herein are system controllers and larger systems incorporating such that can dynamically prioritize critical digital video data streams traveling across a network backbone over other non-priority video data and make the selection of which video streams are to be connected and prioritized through real-time use of video control panel equipment. Detailed information on various example embodiments of the inventions are provided in the Detailed Description below, and the inventions are defined by the appended claims.

Video switching system utilizing a prioritized common network

An apparatus and method for transferring data between a host system and a communication network via a communication module wherein the communication module presents a UART-like interface to the host system. The communication module is comprised of an emulated UART module, a digital signal processor (DSP), and a DSP memory. The emulated UART provides a compatible UART-like front end for interlacing directly with a host system and additionally performs direct memory access-like (DMA) functions enabling the direct transfer of transmit data between the host system and DSP memory that is directly accessible by the DSP for modulation and/or other processing such as data compression. The emulated UART module additionally provides performance features such as adjustable buffering quantity thresholds for triggering interrupts to either the host system or DSP, and pacing features that provide the host system with the appearance and performance of a serialized UART.

UART with direct memory access buffering of data and method therefor

In a system having an DSP, an ASIC and a memory, in which the ASIC generates a number of different competing interrupts for the DSP to service, the ASIC has an interrupt request control module which automatically provides the DSP with a vector pointing to the memory location of the interrupt service routine for the currently pending interrupt request having the highest priority of all pending requests. The DSP reads this vector and uses it to access the interrupt service routine in the memory. Reading of this vector causes the interrupt request to be de-asserted, which causes the next highest priority pending interrupt request to become the highest priority pending interrupt request. As a result, a new vector is presented for the next read by the DSP.

Interrupt request control module with a DSP interrupt vector generator

Growing community of inventors

Kaysville, UT, United States of America

Garn H Morrell