Xilinx, Inc.

Garik Mkrtchyan

Satish B Sivaswamy

Grigor S Gasparyan

Nitin Deshmukh

Guenter Stenz

Chun Zhang

Mehrdad Eslami Dehkordi

Frederic Revenu

Nicholas A Mezei

Frank Mueller

Jinny Singh

Thomas O Satter

Bhasker Pinninti

Ashot Shakhkyan

Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed on one or more processors, cause the one or more processors to perform operations. The operations include generating a plurality of child processes according to a number of a plurality of partitions in an integrated circuit (IC) design for an IC die, each of the plurality of child processes corresponding to and assigned to a respective one of the plurality of partitions. The operations include transmitting each of the plurality of partitions to a respective one of the plurality of child processes for routing, each of the plurality of partitions comprising a placement of components for the IC design. The operations include receiving a plurality of routings from the plurality of child processes. The operations include merging the plurality of routings into a global routing for the IC design by assembling together to form a global routing.

Distributed parallel processing routing

A design tool determines features of a circuit design and applies a first model to the features. The first model indicates a predicted value of a metric based on the plurality of features. The design tool applies an explanation model to the features, and the explanation model indicates levels of contributions by the features to the predicted value of the metric, respectively. The design tool selects a feature of the plurality of features based on the respective levels of contributions and looks up a recipe associated with the feature in a database having possible features associated with recipes. The design tool processes the circuit design according to the recipe into implementation data that is suitable for making an integrated circuit (IC).

Predicting a performance metric based on features of a circuit design and explaining marginal contributions of the features to the prediction

Synthetizing a hardware description language code into a netlist comprising loads and a multi-clock buffer (MBUF). The MBUF receives a global clocking signal and generates a first and a second related clocking signals. The loads are grouped into a first and a second groups receiving the first and the second clocking signals respectively. A first/second clock modifying leaf are placed between a common node and the first/group groups respectively, wherein the common node is positioned closer in proximity to the first/second groups in comparison to a clock source generating the global clocking signal. The first/second clock modifying leaves receive a least divided clocking signal from the MBUF and generate the first/second clocking signals respectively. The least divided clocking signal is routed from the MBUF to the first/second clock modifying leaves. The first/second clocking signals are routed from the first/second clock modifying leaves to the first/second group respectively.

Synchronous clock domain crossing skew optimization and multi-clock buffer (MBUFG)

Performing partition wire assignment for routing a multi-partition circuit design can include performing, using computer hardware, a global assignment phase by clustering a plurality of super-long lines (SLLs) into a plurality of SLL bins, clustering loads of nets of a circuit design into a plurality of load clusters, and assigning the plurality of SLL bins to the plurality of load clusters. For each SLL bin, a detailed assignment phase can be performed wherein each net having a load cluster assigned to the SLL bin is assigned one or more particular SLLs of the SLL bin using the computer hardware.

Partition wire assignment for routing multi-partition circuit designs

Some examples described herein relate to routing in routing elements (e.g., switches). In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to model a communication network among switches interconnected in an array of data processing engines (DPEs), generate routes for an application on the modeled communication network, and translate the routes to a file. Each DPE includes a hardened processor core, a memory module, and one or more of the switches. Each switch includes an input or output port that is capable of being shared by multiple routes. Port(s) of each switch are modeled as respective node(s). Generating the routes includes using an A* algorithm that includes a congestion costing function based on a capacity of respective nodes in the modeled communication network and a cumulative demand for the respective nodes.

Data processing engine (DPE) array routing

Routing a multi-fanout net includes selecting a driver component of the multi-fanout net of a circuit design, wherein the circuit design is specified programmatically, and determining a plurality of targets of the driver component. A source wave is created at each of a plurality of nodes of the driver component. One target is assigned to each source wave. Each source wave is expanded.

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Fremont, CA, United States of America

Garik Mkrtchyan