International Business Machines Corporation

Gareth John Nicholls

Hayden C Cranford, Jr

Vernon Roberts Norman

Martin L Schmatz

James Stephen Mason

Philip J Murfet

Juan Antonio Carballo

Louis C Hsu

Michael Anthony Sorna

Lee Jason Sanders

Karl David Selander

Brian Joel Schuh

Thomas J Bardsley

Matthew R Cordrey-Gale

Mark Keith Elliott

Phil J Murfet

Bobak Modaress-Razavi

Louis Lu-Chen Hsu

Paul Nicholas Cashman

Florent Rostagni

Roderick Guy Charles Moore

Alexander Henry Ainscow

Samuel Taylor Ray

Jon David Garlett

Katja Gebuhr

A method, computer program product, and computer system for copying of data in a storage system between storage drives that have embedded compression. The method includes determining that a copy operation of data is required from a source drive to a target drive and determining that the source drive and the target drive use the same compression algorithm. The method includes: reading the data in a compressed form from the source drive including bypassing a decompression algorithm; transmitting the compressed data from the source drive to the target drive; and receiving and writing the compressed data at the target drive including bypassing a compression algorithm at the target drive.

Copying of data in a storage system between storage drives that have embedded compression

Provided is a computer-implemented method, system, and apparatus for a visual identification of a port and a previously connected cable of a link in a network environment including a network switch or a network device. The apparatus having an LED arrangement at a port assembly configured for illumination at the port and configured to provide illumination via the cable to a remote end of the link. An identifier providing component controls the LED arrangement based on a unique attribute of the link including: detecting a status change of a link; obtaining the unique attribute related to the link from a layer of a protocol received on both ends of the link; selecting an identifier based on the unique attribute related to the link; and instructing the LED arrangement to be configured to provide a light output of the selected identifier.

Visual identification of a port and a cable in a network

Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.

Method and arrangements for link power reduction

A receiver for a data communications system comprises: a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.

Data communications systems

A machine-readable medium thereupon stored a design structure; the design structure includes a receiver for a data communications system. The receiver includes a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.

Structure for data communications systems

Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.

One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery

A method, circuit and system for altering the power consumption in communication links. A type of noise and an amount of jitter in a signal transmitted across a communication link is measured. Upon determining the contribution of the measured noise to the measured jitter in the signal, the measured noise is classified based on such contribution and the intensity of the measured jitter. The power consumption in a component(s) of the communication link may be adjusted based on the classification of the measured noise. For example, if the measured noise is classified as being a low amount of noise, then the power consumption of the component(s) may be reduced such as by lowering the voltage of the power supply and/or reducing the complexity of the circuitry. By reducing the power consumption when the communication link is not subject to the worst-case condition, a savings in power consumption may be made.

Altering power consumption in communication links based on measured noise

Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.

method for providing automatic adaptation to frequency offsets in high speed serial links

Methods and arrangements for link power reduction

A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages () connected in parallel with each amplifier stage having a gain control means. Input signal means () are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage () are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (). The gain of the amplifier array has a range from a low gain setting with a first amplifier stage () enabled, through increasing gain settings as the gain of the first amplifier stage is increased from a minimum to a maximum gain, a second amplifier stage () can then be enabled in addition to the first amplifier stage and the gain of the second amplifier stage increased from a minimum to a maximum gain, further amplifier stages are enabled as available up to a maximum gain setting for the amplifier array. Each amplifier stage that is enabled has a decreasingly attenuated input signal and a final amplifier stage to be enabled has a full input signal ().

Variable gain amplifier

A method, in an oversampling clock and data recovery system, for detecting that sampling is stuck taking place at a data edge, by detecting a data edge in an early or a late region relative to a good region and incrementing a stuck early or stuck late counter; and if one counter reaching a maximum, setting a condition indicating that sampling is stuck taking place at a data edge. If a data edge is detected in the good region, or in each of an early and a late region in a single data period, the stuck counters are reset to zero. The detection of which stuck counter has reached a maximum can cause the moving of a sampling clock forward or backward, ending when a data edge occurs in a good region, or in each of an early region and a late region in a single data period.

Fast detection of incorrect sampling in an oversampling clock and data recovery system

Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.

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Brockenhurst, United Kingdom

Gareth John Nicholls