Sharp Kabushiki Kaisha Corporation

Sharp Life Science Corporation

Gareth John

Patrick Zebedee

Michael James Brownlow

Benjamin James Hadwen

Graham Andrew Cairns

Harry Garth Walton

Adrian Marc Simon Jacobs

Jason Roderick Hector

Jeremy Lock

Jaganath Rajendra

Tim Gasser

A shift register includes cascade-connected stages, each of which includes a data latch and an output stage. In at least one embodiment, the latch has a single data input which, in use, receives a date signal from a preceding or succeeding stage. The output stage includes a first switch, which passes a clock signal to the stage output when the output stage is activated by the latch. The output stage also comprises a second switch, which passes the lower supply voltage to the stage output when the output stage is inactive.

Shift register and active matrix device

A static random-access memory (SRAM) cell which includes: a sampling switch and a feedback switch; and a first inverter and a second inverter connected in series whereby an output of the first inverter is connected to an input of the second inverter. An input of the first inverter is connected to a data input of the SRAM cell via the sampling switch, and to a data output of the SRAM cell independent of the feedback switch, an output of the second inverter is connected to the input of the first inverter via the feedback switch, and first and second clock inputs of the SRAM cell are configured to control the sampling switch and the feedback switch, respectively.

Static random-access cell, active matrix device and array element circuit

A serial-to-parallel converter which includes n input latching elements; k intermediate latching elements, and n output latching elements configured to sample outputs of the k intermediate latching elements and a remaining (n&#x2212;k) input latching elements of the n input latching elements, respectively, after the nth data of the n successive data has been sampled by the nth input latching element and before the kth data of a next n successive data in the serial input data stream has been sampled by the kth input latching element, wherein the n input latching elements and the k intermediate latching elements are transparent for one state of their clock input, and n and k are positive integers, where n&#x3e;k.

Serial-to-parallel converter, and display device incorporating the same

In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.

Drive circuit, a display device provided with the same

An active matrix electrowetting on dielectric (AM-EWOD) device which includes a plurality of array elements configured to manipulate one or more droplets of fluid on an array, each of the array elements including a corresponding array element circuit. Each array element circuit includes a top substrate electrode and a drive electrode between which the one or more droplets may be positioned; circuitry configured to write data to the corresponding array element by selectively applying to the drive electrode either: (i) a time-varying voltage waveform Vof amplitude Vand period t; or (ii) a time-varying voltage waveform V, the logical inverse of V, and applying to the top substrate electrode the time-varying voltage waveform V+V, where Vrepresents an offset voltage signal which may have AC and/or DC components and may equal zero.

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Berkshire, United Kingdom

Gareth John