Arm Limited

Neem Biotech Limited

Mootral Sa

Gareth James Evans

Andrew Brookfield Swaine

Matthew Lucien Evans

Adam James McNeeney

Robert Alun Saunders

Jonathan Curtis Beard

Andrew John Turner

Anthony Jebson

Alexander Donald Charles Chadwick

David Michael Williams

Carl Jorg Graz

An apparatus comprises memory access circuitry to access a memory system; a plurality of memory mapped registers, including at least an insert register and a producer pointer register; and control circuitry to perform an insert operation in response to receipt of an insert request from a requester device sharing access to the memory system. The insert request specifies an address mapped to the insert register and an indication of a payload. The insert operation includes controlling the memory access circuitry to write the payload to a location in the memory system selected based on a producer pointer value stored in the producer pointer register, and updating the producer pointer register to increment the producer pointer value.

Insert operation

A method and apparatus for simulating target program code on a host data processing apparatus, the simulation mapping load-exclusive instructions in the target program code to load instructions, and mapping store-exclusive instructions in the target program code to compare-and-swap instructions.

Simulation of exclusive instructions

A data processing apparatusincludes bridge circuitrywhich serves to translate memory transactions of a first type (AXI) into memory transactions of a second type (PCI Express). The bridge circuitry includes translation circuitrywhich maps at least some of the bits of attribute data of a memory transaction of the first type to unused bits within the significant bits of an address of the second type, which are unused to represent significant bits of the address of memory transactions of the first type.

Bridge circuitry for translating between memory transactions of first type and memory transactions of a second type

An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus including at least one physical processing unit configured to run at least one of a plurality of virtual processors and a memory. The interrupt controller includes redistribution circuitry with at least one data store corresponding to the unit, the data store storing a pointer to a virtual pending table storing currently pending virtual interrupts for a virtual processor currently running on the corresponding unit and a pointer to a pending table configured to store currently pending physical interrupts for the corresponding unit and an input configured to receive a virtual interrupt for interrupting a virtual processor. Control circuitry is configured to add the virtual interrupt to the virtual pending table and to store the virtual interrupt in the virtual pending table for the virtual processor that is stored in the memory.

Handling and routing interrupts to virtual processors

Growing community of inventors

Sandhurst, United Kingdom

Gareth James Evans