Arm Limited

Altera Corporation

Gareth Duncan

David Francis McHale

Rahoul Kumar Varma

Mike Livesley

Marc Richard Wicks

Steven Perry

Methods and systems are provided for a message network interface unit (a message interface unit), coupled to a processor, that is used for allowing the processor to send messages to a hardware unit. Methods and systems are also provided for a message interface unit, coupled to a processor, that is used for allowing a processor to receive messages from a hardware unit. The message network interface unit described herein may allow for the implementation data-intensive, real time applications, which require a substantially low message response latency and a substantially high message throughput.

Processor to message-based network interface using speculative techniques

A data processing apparatus is provided, which is operable to access data values associated with a respective address values. The data processing apparatus has: a processor; a main memory having a secure data values region; a cache; and cache interface logic having data transaction logic and security determination logic. The data transaction logic receives from the processor a data access request for accessing data in cache. The data access request has an associated address value and a security attribute. If the security attribute indicates that the request is a non-secure data-access request, the security determination logic determines, via a data region allocation table, whether the request is associated with the secure data values region of main memory and the non-secure data access request is allowed to complete if it is not associated with the secure data region.

Data processing apparatus security

The present invention provides a data processing apparatus and method for storing trace data. The data processing apparatus comprises a bus operable to interconnect a number of master devices and slave devices to enable transactions to be routed between the master and slave devices. Each master device is able to initiate a transaction, with the transaction specifying a transaction address. A cache is interposed between at least one of the master devices and the bus and is operable to receive the transaction issued by that master device. The cache has a cache memory and a cache controller operable to control access to the cache memory. The cache controller comprises caching logic operable to selectively cache a data value of the transaction at a location in the cache memory chosen dependent on the transaction address. Control storage is provided identifying a trace address range specifying a trace region. Further, trace logic is provided which is operable to selectively generate as trace data one or more attributes associated with the transaction and to provide in association with that trace data a trace address selected from the trace address range. The caching logic is then operable to store the trace data at a location in the cache memory chosen dependent on the trace address. In this way, the cache can be used in a flexible manner to not only act as a normal cache but also to selectively store within the cache trace data.

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Maidenhead, United Kingdom

Gareth Duncan