Xilinx, Inc.

Gareth David Edwards

Stuart Alan Nisbet

Martin B Rhodes

Richard P Burnley

Robert Yin

Douglas Michael Grant

Hamish T Fallside

Nicholas McKay

Martin Sinclair

Nathan A Lindop

Ting Yun Kao

Allan W Fyfe

David Taylor

Mark R Nethercot

Duncan Andrew Cockburn

A method for computing a X-bit cyclical redundancy check (CRC-X) frame value for a data frame transmitted over a N-bit databus is provided. The method includes receiving a N-bit data input with an end-of-frame for the data frame at bit position M on the N-bit databus, performing a bitwise XOR on X most significant bits of the N-bit data input with a CRC-X feedback value to form a first N-bit intermediate data. The method also includes shifting the first N-bit intermediate data by M bit positions to align the end-of-frame of the data frame with a least significant bit (LSB), and padding M number of zero bits to a most significant bit (MSB) of the first N-bit intermediate data to form a second N-bit intermediate data.

Method and implementation of cyclic redundancy check for wide databus

A test environment for performing verification on a parameterizable circuit design can include a test harness specifying a first instance of a device under test characterized by a first parameterization and at least a second instance of the device under test characterized by at least a second parameterization. The test environment further can include a hardware verification language shell configured to randomly generate signals which indicate one of the instances and provide the signals to the test harness. The test harness selects one of the instances according to the signals.

One-pass method for implementing a flexible testbench

A method is provided to incorporate information currently known about an integrated circuit's design, including peripheral components that share the same printed circuit board (PCB) with the integrated circuit, to automate a clock signal instantiation and routing solution to realize a comprehensive design. The information derived from a hardware design synthesis tool includes the existence of PCB resources, such as fixed-frequency oscillators, that may co-exist with a particular integrated circuit, such as a programmable logic device (PLD). Other derived information includes details concerning clock modules and cores that may exist within the PLD in accordance with the PLD's design specification. Once the information that describes the PLD and its environment is known, the information is utilized to automatically instantiate resource interconnect cores and automatically generate connections between the fixed-frequency oscillators, resource interconnect cores, and PLD implemented cores that are contained within the design.

Method of automating clock signal provisioning within an integrated circuit

A method of enabling the generation of reset signals in an integrated circuit is disclosed. The method comprises receiving information related to reset ports for a plurality of intellectual property cores in a design tool; providing an intellectual property core comprising a reset logic circuit adapted to generate a plurality of reset signals for the plurality of intellectual property cores; and generating, by the design tool, configuration data enabling programmable interconnects to couple a first reset signal of the plurality of reset signals to a first intellectual property core of the plurality of intellectual property cores and a second reset signal of the plurality of reset signals to a second intellectual property core of the plurality of intellectual property cores.

Method of enabling the generation of reset signals in an integrated circuit

A receive-side client interface for a media access controller embedded in an integrated circuit having programmable circuitry is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. The receive-side datapath is configured to operate at two frequencies to accommodate the programmable circuitry in the integrated circuit.

Network media access controller embedded in a programmable device&#x2014;receive-side client interface

A media access system in an integrated circuit device having programmable resources for interfacing to a network. The media access system has at least one embedded media access controller configured to provide access to and from the network via a physical layer interface, programmable resources coupled to the embedded controller via a client interface, tie-off pin inputs coupled to the embedded controller for receiving a configuration vector for configuring the embedded controller without having to use a microprocessor for such configuration with the client interface being for communication between the embedded controller and the programmable resources for access to and from the network, and the embedded controller including a multi-mode interface coupled to the client interface for coupling to the programmable resources, the multi-mode interface including a plurality of Media Independent Interface modes, the multi-mode interface configured to be coupled to the physical layer interface.

Embedded network media access controller

A method and apparatus for improving enforcement of the time-limited operation of a programmable device. Two random number generators, e.g., linear feedback shift register (LFSR) circuits, are utilized in which a first LFSR provides free-running capability, while a second LFSR provides time-sensitive capability. The states of the two LFSR circuits are compared by various portions of the programmable device at each state transition in order to obtain authorization to continue operation. Authorized operation continues as long as the states of both LFSRs are equivalent, or at least equivalent, within a given phase offset. Once a terminal count of the time-sensitive LFSR is reached, then authorization for continued operation ends and at least a portion of the programmable device is disabled.

Method and apparatus for protection of time-limited operation of a circuit

A media access controller system embedded in an integrated circuit is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in an integrated circuit. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.

Network media access controller embedded in an integrated circuit host interface

Measuring transit time across an asynchronous first-in-first-out (FIFO) memory can include sampling an indication of a value of a read pointer of the FIFO memory at a sampling frequency that exceeds a frequency of a read clock and a write clock of the FIFO memory. An indication of a value of a write pointer of the FIFO memory can be sampled at the sampling frequency. For each sampling period, a measure of occupancy of the FIFO memory can be calculated according to a sampled pair including the indication of the value of the read pointer and the indication of the value of the write pointer. The measure of occupancy can be averaged over a predetermined number of cycles of the sampling frequency. The averaged measure of occupancy can be output as an indication of transit time across the FIFO memory.

Determining transit time across an asynchronous FIFO memory by measuring fractional occupancy

A transmit-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a transmit engine. A transmit-side datapath is coupled to the media access controller core. The transmit-side datapath is configured to operate at two frequencies to accommodate the programmable logic in the integrated circuit.

Network media access controller embedded in a programmable logic device&#x2014;transmit-side client interface

A media access controller system embedded in a programmable logic device is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in a programmable logic device. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.

Network media access controller embedded in a programmable logic device&#x2014;host interface

A receive-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. The receive-side datapath configured is configured to operate at two frequencies to accommodate the programmable logic in the integrated circuit.

Network media access controller embedded in a programmable logic device&#x2014;receive-side client interface

A statistics interface for a media access controller is described. The media access controller core includes a receive engine configured to provide a receive statistics vector associated with receive traffic. The receive engine is configured to output the receive statistics vector within an inter-frame gap over a number of receive clock cycles, where a portion of the receive statistics vector is provided with each clock cycle of the receive clock cycles.

Network media access controller embedded in a programmable logic device&#x2014;statistics interface

An aspect of the invention is physical layer interface for a network interface including a plurality of input/output pins. The input/output pins are coupled for being multiplexed into a physical layer interface selected from among a Reduced Gigabit Media Independent Interface and a Gigabit Media Independent Interface. The input/output pins internal to a programmable logic device are for access to and from a processor block located in the programmable logic device.

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Edinburgh, United Kingdom

Gareth David Edwards