Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Garam Kim

Jihoon Kim

Junghwan Choi

Jisoo Kim

Junyoung Park

Sangkwon Moon

Hyunggon Kim

Hyunkyo Oh

Jindo Byun

Joonsuc Jang

Hyunyoon Cho

Joohwan Kim

Youngjun Hwang

Woohyun Kang

Eunseok Shin

Wontaeck Jung

Jisang Lee

Hun-Bae Kim

Jin Gu Jeong

Yong-Gu Kang

A storage device according to an embodiment includes a memory device configured to apply a first program voltage and a first verification voltage to a first word line and output, based on a program state of each of a plurality of memory cells connected to the first word line, a speed information representing a speed characteristic of each of the plurality of memory cells; and a memory controller configured to determine at least one memory cell to be programmed into a predetermined program state; determine, among the at least one memory cell, at least one target memory cell having a first speed characteristic based on the speed information; and perform a state-shaping operation to convert a data corresponding to the predetermined program state for the at least one target memory cell into a value corresponding to a program state different from the predetermined program state.

Storage device for performing a state shaping operation on data based on a speed characteristic of a memory cell and operation method thereof

A transmitter configured to receive first to N-th data in parallel and sequentially output the first to N-th data in response to first to N-th clock signals having different phases from each other, where N is an integer of at least 2, the transmitter including first to N-th data selectors including a first data selector and a second data selector in correspondence to the first to N-th data, each of the first to N-th data selectors being configured to perform a logical operation on one of the first to N-th data and the first to N-th clock signals and output a plurality of data selection signals, a first pre-driver in correspondence to at least two data selectors among the first to N-th data selectors, the first pre-driver being configured to receive the plurality of data selection signals from the at least two data selectors.

Transmitter, memory device and semiconductor device including the transmitter

A display apparatus including: a display panel including an emission line and a pixel electrically connected to the emission line; an emission driver configured to output an emission signal to the emission line; and a driving controller configured to determine a light emission cycle, wherein the light emission cycle is a number of light emissions in a single frame of the emission signal, wherein the driving controller is configured to determine a luminance according to a user luminance setting and a grayscale value of input image data, to determine the light emission cycle corresponding to a range of the luminance and to determine an off ratio according to the luminance, wherein the off ratio is a ratio of turned-off gate lines to a total number of the gate lines.

Display apparatus and a method of driving a display panel using the same

A memory device includes a memory cell array including a plurality of memory cells; a voltage generator configured to generate voltages used for a program operation and a verify operation for the memory cells; and control logic configured to perform a plurality of program loops while writing data to the memory cell array, such that first to N-th (e.g., N&#x3e;=1) program loops including a program operation and a verify operation are performed and at least two program loops in which the verify operation is skipped are performed when a pass/fail determination of the program operation in the N-th program loop indicates a pass.

Memory device with conditional skip of verify operation during write and operating method thereof

A memory device includes a memory cell array including M memory cells connected to one bit line and configured to distributively store N-bit data, where N is a natural number of 2 or more and M is a natural number of 2 or more and less than or equal to N, the M memory cells including a first memory cell and a second memory cell having different sensing margins, and a memory controller including a page buffer, the memory controller configured to distributively store the N-bit data in the M memory cells and to sequentially read data stored in the M memory cells to obtain the N-bit data, and an operation logic configured to execute an operation using the N-bit data, the memory controller configured to provide different reading voltages to the first memory cell and the second memory cell.

Memory device, and electronic device including the same

Growing community of inventors

Suwon-si, South Korea

Garam Kim