Samsung Electronics Co., Ltd.

Garam Choi

Hundae Choi

Sungho Jang

Wookrae Kim

Yonghun Kim

Jinseob Kim

Jinyong Kim

Kihan Kim

Daehoon Han

Jaewoo Lee

Taejoong Kim

Hojun Chang

Changhoon Choi

Jihoon Na

Younguk Jin

An EUV photomask inspection apparatus includes a plurality of optical systems respectively forming different confocal points in a mask structure including an EUV photomask and a pellicle on the EUV photomask. A first optical system among the plurality of optical systems includes a first light source emitting first light having a wavelength in a visible light range, a beam splitter transmitting or reflecting the first light, an objective lens configured to allow the first light to pass through at least a portion of the mask structure to form a first focus in the mask structure, a first light detector configured to detect first reflected light reflected from the mask structure by the incident first light, and a pinhole plate in front of the first light source. The first light detector includes a detection module including a PMT and an APD, and a thermoelectric cooling module.

EUV photomask inspection apparatus

A semiconductor measurement apparatus includes an illumination unit including a light source and at least one illumination polarization element, a light receiving unit including at least one light-receiving polarization element disposed on a path of light reflected by a sample, and an image sensor positioned to receive light passing through the at least one light-receiving polarization element and configured to output an original image, and a control unit configured to determine, by processing the original image, a selected critical dimension among critical dimensions of a structure included in a region of the sample. The control unit is configured to obtain a plurality of sample images by selecting regions of the original image in which a peak due to interference appears, to determine a plurality of elements included in a Mueller matrix using the plurality of sample images, and to determine the selected critical dimension based on the plurality of elements.

Semiconductor measurement apparatus

A semiconductor measurement apparatus may include an illumination unit configured to irradiate light to the sample, an image sensor configured to receive light reflected from the sample and output multiple interference images representing interference patterns of polarization components of light, an optical unit in a path through which the image sensor receives light and including an objective lens above the sample, and a control unit configured to obtain, by processing the multi-interference image, measurement parameters determined from the polarization components at each of a plurality of azimuth angles defined on a plane perpendicular to a path of light incident to the image sensor. The control unit may be configured to determine a selected critical dimension to be measured from a structure in the sample based on measurement parameters. The illumination unit and/or the optical unit may include a polarizer and a compensator having a ¼ wave plate.

Provided are a memory device and a method for training per-pin operation parameters. A memory device includes a plurality of on-die termination (ODT) circuits, an impedance control (ZQ) calibration circuit configured to output a first code signal and a second code signal, and a per-pin calibration circuit. The per-pin calibration circuit may be configured to select one signal pin from among the plurality of signal pins, to compare a first input voltage level of the selected signal pin with a second input voltage level of each of the other ones of the plurality of signal pins, to generate a per-pin ODT code signal for each of the plurality of signal pins, to combine the per-pin ODT code signal with the first code signal or the second code signal, and to provide the combined per-pin ODT code signal to the respective ODT circuits.

Memory device and method for training per-pin operation parameters

A semiconductor chip includes a write clock buffer, a voltage regulator, a process calibration circuit and a temperature calibration circuit. The voltage regulator generates plural regulated voltages. The process calibration circuit output one of the regulated voltages as a bias voltage of the write clock buffer, depending on a process variation of the semiconductor chip. The temperature calibration circuit track a temperature variation of the semiconductor chip in real time, performs analog calibration on the bias voltage from the process calibration circuit in real time depending on a result of the tracking, and outputs the analog-calibrated bias voltage to the write clock buffer.

Semiconductor chip capable of calibrating bias voltage supplied to write clock buffer regardless of process variation and temperature variation, and devices including the same

A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code.

Duty adjustment circuit, and delay locked loop circuit and semiconductor memory device including the same

A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.

Multi-phase clock generator, memory device including multi-phase clock generator, and method of generating multi-phase clock of memory device

A delay circuit of a delay-locked loop (DLL) circuit includes: a phase splitter configured to split a phase of a reference clock signal to output a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees; a logic gate configured to delay the second reference clock signal to output a delayed reference clock signal; and a delay line circuit including a plurality of delay cells that are cascade-connected, the delay line circuit configured to delay the first reference clock signal and the delayed reference clock signal based on a control code set, and to output a first delayed clock signal and a second delayed clock signal having a delay amount corresponding to a delay of one logic gate included in the plurality of delay cells.

Delay circuit of delay-locked loop circuit and delay-locked loop circuit

A delay locked loop circuit and a semiconductor memory device are provided. The delay locked loop circuit includes a phase detection and delay control circuit configured to detect a phase difference between a first internally generated clock signal the feedback clock signal to generate a first phase difference detection signal in response to a first selection signal being activated, to detect a phase difference between a second internally generated clock signal and the feedback clock signal to generate a second phase difference detection signal in response to a second selection signal being activated, and to change a code value in response to the first phase difference detection signal or the second phase difference detection signal.

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Hwaseong-si, South Korea

Garam Choi