Advanced Micro Devices Corporation

Ati Technologies Ulc

Nvidia Corporation

Gaojian Cong

Jing Liu

Kostantinos Danny Christidis

HaiKun Dong

MinHua Wu

Ling-Ling Wang

Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.

Duplicated registers in chiplet processing units

The present invention relates to scannable D flip-flops, which are improved to solve the problem of the conventional designs and provides a small and fast scannable D flip-flop without compensating its testability. The embodiment of the present invention provides a scannable D flip-flop, comprising a source coupled logic, comprising a trigger circuit for reading a clock input; a scannable input circuit coupled to the trigger circuit having four NMOS transistors; a first feedback circuit for a first output; and a second feedback circuit for a second output; a latch circuit coupled to the source coupled logic; and an output buffer coupled to the latch circuit. Another embodiment of the present invention provides a scannable D flip-flop, comprising: a cascade dynamic logic, comprising: a first stage circuit; a second stage circuit coupled to the first stage circuit; a third stage circuit coupled to the second stage circuit; and a scannable input circuit coupled to the first stage circuit having four NMOS transistors for reading a data input and scannable inputs; a latch circuit coupled to the second stage circuit; and an output buffer coupled to the latch circuit.

Scannable D flip-flop

Growing community of inventors

Shanghai, China

Gaojian Cong