Taiwan Semiconductor Manufacturing Comp. Ltd.

Gao-Ming Wu

Katherine H Chiang

Chung-Te Lin

Chien-Hao Huang

Yun-Feng Kao

Han-Ting Tsai

Li-Shyue Lai

Ming-Yen Chuang

Provided are a transistor structure and a method of forming the same. The transistor structure includes a gate electrode; a gate dielectric layer, disposed on the gate electrode; an active layer, disposed on the gate dielectric layer; a pair of source/drain (S/D) features, disposed on the active layer; and an isolation structure, laterally surrounding the pair of S/D features, wherein the isolation structure at least comprises a blocking layer and an upper dielectric layer on the blocking layer.

Transistor structure and method of forming the same

A three-dimensional integrated structure and the manufacturing method(s) thereof are described. The three-dimensional integrated structure includes a substrate having conductive features therein, and a component array disposed over the substrate and on the conductive features. The component array includes a metallic material layer and capacitor structures separated by the metallic material layer. Each of the capacitor structures includes a first metallic pillar, a first dielectric sheath surrounding the first metallic pillar, a second metallic sheath surrounding the first dielectric sheath, and a second dielectric sleeve surrounding the second metallic sheath. The metallic material layer laterally encapsulates the capacitor structures.

Three-dimensional integrated structure and manufacturing method thereof

A two-dimensional array of discrete dielectric template structures is formed over a substrate. A first dielectric spacer matrix may be formed in lower portions of the trenches between the discrete dielectric template structures. A second dielectric spacer matrix layer may be formed in upper portions of the trenches. A pair of a source cavity and a drain cavity may be formed within a volume of each of the discrete dielectric template structures. A source electrode and a drain electrode may be formed in each source cavity and each drain cavity, respectively. The gate electrodes may be formed prior to, or after, formation of the two-dimensional array of discrete dielectric template structures to provide a two-dimensional array of field effect transistors that may be connected to, or may contain, memory elements.

Self-aligned multilayer spacer matrix for high-density transistor arrays and methods for forming the same

Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes gate electrodes and first insulation patterns laterally disposed and alternately arranged on a substrate, a gate dielectric layer disposed on the gate electrodes and the first insulation patterns, at least one channel pattern disposed on the gate dielectric layer, source electrodes and drain electrodes laterally disposed and alternately arranged on the channel pattern, and second insulation patterns disposed on the channel pattern between the source and drain electrodes. Besides, from a top view, each of the drain electrodes is overlapped with one of the first insulation patterns.

Semiconductor structures and methods of forming the same

An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.

Cavity in metal interconnect structure

A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.

Semiconductor device and manufacturing method thereof

Provided are a semiconductor device and method of forming the same. The semiconductor device includes active components and a first barrier pattern. The active components are on a substrate. Each of the active components includes base insulation patterns on the substrate, gate electrodes on the substrate and spaced apart from each other with the base insulation patterns interposed therebetween, a gate dielectric layer on the gate electrodes and the base insulation patterns, a channel pattern on the gate dielectric layer, source electrodes on the channel pattern and spaced apart from each other, a drain electrode on the channel pattern and between the source electrodes, and second insulation patterns between the source electrodes and the drain electrode. The first barrier pattern disposed on the gate dielectric layer surrounds the channel patterns, the source electrodes, the drain electrodes, and the second insulation patterns of each of the active components.

Semiconductor device including an active component and a barrier pattern surrounding the active component and method of forming the same

A semiconductor structure, comprising a substrate and an interconnect layer disposed over a substrate and extending across a memory region and a logic region. The interconnect layer comprises a plurality of tower structures disposed in the interconnect layer within the memory region. Each tower structure comprises at least one metal interconnect structure and a magnetic tunnel junction (MTJ) structure stacked on the metal interconnect structure. The plurality of tower structures are arranged on the substrate in a XY staggered pattern. The at least one metal interconnect structure and the magnetic tunnel junction (MTJ) structure in each tower structure are substantially symmetric along a stacking direction.

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Hsinchu, Taiwan

Gao-Ming Wu