Qualcomm Incorporated

Gang Zhang

Yiping Han

Frederic Bossu

Tsai-Pi Hung

Yung-Chung Lo

Jae-Hong Chang

Jeremy Darren Dunworth

Yang Xu

Prasad S Gudem

Timothy Paul Pals

Hong Sun Kim

Hung-Chuan Pai

Jin Wook Kim

Abhishek Jajoo

A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), a second voltage regulator to regulate a second input voltage to the second voltage regulator, and a switch circuit to selectively activate at least one of the first voltage regulator or the second voltage regulator. In one aspect, the second voltage regulator includes an N-type metal-oxide-semiconductor (NMOS). In one aspect, the second voltage regulator comprises a two-stage operational transconductance amplifier (OTA) circuit. In an aspect, the first voltage regulator is coupled to the second voltage regulator.

On-chip dual-supply multi-mode CMOS regulators

A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), and a second voltage regulator to regulate a second input voltage to the second voltage regulator, the second voltage regulator including an N-type metal-oxide-semiconductor (NMOS). In an aspect, the first voltage regulator is coupled to the second voltage regulator.

Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit that is configured to receive a divided signal produced by the frequency divider. The frequency divider can also include a frequency multiplier that is configured to produce an output signal based on the delayed signal produced by the delay circuit, wherein the delay circuit is configured to receive the output signal.

Reconfigurable fractional divider

The LC tank of a VCO includes a main varactor circuit and temperature compensation varactor circuit coupled in parallel with the main varactor circuit. The main varactor is used for fine tuning. The temperature compensation varactor circuit has a capacitance-voltage characteristic that differs from a capacitance-voltage characteristic of the main varactor circuit such that the effects of common mode noise across the two varactor circuits are minimized. The LC tank also has a plurality of switchable capacitor circuits provided for coarse tuning. To prevent breakdown of the main thin oxide switch in each of the switchable capacitor circuits, each switchable capacitor circuit has a capacitive voltage divider circuit that reduces the voltage across the main thin oxide switch when the main switch is off.

Temperature compensation and coarse tune bank switches in a low phase noise VCO

A loop filter with noise cancellation includes first and second signal paths, an operational amplifier (op-amp), and a noise cancellation path. The first signal path provides a first transfer function (e.g., a lowpass response) for a first signal. The second signal path provides a second transfer function (e.g., an integration response) for a second signal. The second signal is a scaled version of, and smaller than, the first signal by a factor of alpha, where alpha is greater than one. A capacitor in the second signal path may be scaled smaller by a factor of alpha. The op-amp couples to the first and second signal paths and facilitates summing of signals from the first and second signal paths to generate a control signal having op-amp noise. The noise cancellation path couples to the op-amp and provides a noise cancellation signal used to cancel the op-amp noise in the control signal.

Loop filter with noise cancellation

A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digital values by a charge pump and an Analog-to-Digital Converter (ADC). The stream of digital values is supplied to the digital loop filter which in turn supplies digital tuning words to the DCO. A number of types of ADCs can be used for the ADC including a continuous-time delta-sigma oversampling Digital ADC and a Successive Approximation ADC. The voltage signal on the charge pump output is a small amplitude midrange voltage signal. The small voltage amplitude of the signal leads to numerous advantages including improved charge pump linearity, reduced charge pump noise, and lower supply voltage operation of the overall PLL.

ADC-based mixed-mode digital phase-locked loop

A frequency synthesizer circuit is disclosed. The frequency synthesizer circuit includes a comparator circuit coupled to a reference clock and a phase-corrected output signal. The frequency synthesizer circuit also includes a loop filter coupled to the comparator circuit. The frequency synthesizer circuit also includes an oscillator coupled to the loop filter. The frequency synthesizer circuit also includes a fractional divider coupled to an output of the oscillator. The frequency synthesizer circuit also includes phase correction circuitry that corrects a phase of an output of the fractional divider to produce the phase-corrected output signal.

Phase locked loop with phase correction in the feedback loop

Techniques for generating oscillator signals in a wireless communication device are described. A phase-locked loop (PLL) may be used to generate an oscillator signal for a selected frequency channel. Different PLL settings may be used for the blocks in the PLL for different frequency channels. The different PLL settings may be for different PLL loop bandwidths, different amounts of charge pump current, different frequency equations associated with different sets of high and low divider ratios, different frequency division schemes associated with different prescaler ratios and/or different integer divider ratios, high side or low side injection for a super-heterodyne receiver or transmitter, and/or different supply voltages for one or more circuit blocks such as an oscillator. A suitable set of PLL settings may be selected for each frequency channel such that adverse impact due to spurs can be mitigated.

Oscillator signal generation with spur mitigation in a wireless communication device

A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.

Phase to digital converter in all digital phase locked loop

The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.

Delta-sigma modulator clock dithering in a fractional-N phase-locked loop

Techniques for achieving linear operation for a phase frequency detector and a charge pump in a phase-locked loop (PLL) are described. The phase frequency detector receives a reference signal and a clock signal, generates first and second signals based on the reference and clock signals, and resets the first and second signals based on only the first signal. The first and second signals may be up and down signals, respectively, or may be down and up signals, respectively. The phase frequency detector may delay the first signal by a predetermined amount, generate a reset signal based on the delayed first signal and the second signal, and reset the first and second signals with the reset signal. The charge pump receives the first and second signals and generates an output signal indicative of phase error between the reference and clock signals.

Linear phase frequency detector and charge pump for phase-locked loop

Design techniques for a low-power asynchronous counter. In an exemplary embodiment, the clock inputs and signal outputs of a plurality of flip-flops are serially concatenated to implement an asynchronous counting mechanism. The signal outputs of the plurality of flip-flops are sampled by successively delayed versions of a reference signal. Further design techniques for generating successively delayed versions of the reference signal are disclosed. In an exemplary embodiment, the asynchronous counting techniques may be utilized in a high-speed counter for a digital-phase locked loop (DPLL).

Low-power asynchronous counter and method

Techniques for converting an accumulated phase of a signal into a digital value in a digital phase-locked loop (DPLL). In an exemplary embodiment, a signal is coupled to a divide-by-N module that divides the frequency of the signal down by a divider ratio N. The divided signal is input to a delta phase-to-digital converter, which measures the phase difference between a rising edge of the divided signal and a rising edge of a reference signal. The accumulated divider ratios and the measured phase differences are combined to give an accumulated digital phase. Further techniques for varying the divider ratio N using a sigma-to-delta modulator are disclosed.

Accumulated phase-to-digital conversion in digital phase locked loops

A phase-locked loop includes a phase-to-digital converter portion as well as a novel correction portion. The phase-to-digital converter (PDC) portion outputs a stream of first phase error words. The novel correction portion receives the first phase error words and generates a stream of second phase error words that is supplied to a loop filter. The PDC portion has a phase-to-digital transfer function that exhibits certain imperfections. In a first example, the correction portion determines an average difference between pairs of first phase error words, and uses this average difference to normalize the first phase error words to correct for changes in PDC portion transfer function slope due to changes in delay element propagation delay. In a second example, the correction portion corrects for gain mismatches in PDC portion transfer function. In a third example, the correction portion corrects for offset mismatches in PDC portion transfer function.

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San Diego, CA, United States of America

Gang Zhang