International Business Machines Corporation

Gang Zhang

Hideaki Komatsu

Hitomi Takahashi

Masana Murase

Shu Shimizu

Akashi Satoh

Sumio Morioka

A technique for increasing the speed of parallel running of logical processes without sacrificing the accuracy of data update timing in a parallel discrete event simulation system. A logical process involving a longer receiving time lag than that of sending is executed by an amount of initial shift for a predetermined period before the simulation. The initial shift is set to be one-half of a value of difference between the receiving time lag and the sending time lag. The logical process executed with timing displaced by the amount of initial shift runs by exchanging null messages with each other. Each null message is delivered to a correspondent logical process after the predetermined time lag, and each logical process further sends the correspondent logical process a null message upon receipt of the null message. Thus, there is a progression of simulation by synchronizing them through the null messages.

Simulation execution method, program, and system

A method converts a plurality of functional blocks into linear blocks such that the nonlinear blocks are divided into a plurality of states through switched linearization. The plurality of states generated by said switched linearization is then transitioned selectively based on a predetermined operational scenario. Each state is then tested separately to ensure that implementation of the states are safe. A first guard block is provided when a state is deemed unsafe such that the first guard block is enabled to cause a system shutdown so as to prevent further processing that can cause an unsafe result.

Control system design simulation using switched linearization

To provide a high-speed combinational circuit including an S-Box and a method for creating an RO-BDD that defines a configuration of the combinational circuit. The combinational circuit includes a number of independent selector groups for each generating an output bit separately, the number corresponding to number of the output bits, and a driver chain for supplying a primary input to each of the selector groups, in which each of the selector groups includes a plurality of selectors connected to each other to form a number of stages, the number of stages being equal to or less than number of bits of the primary input, and a select signal for the selectors in each stage is driven by one primary input.

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Kanagawa, Japan

Gang Zhang