Silicon Laboratories Inc.

Gang Yuan

Axel Thomsen

Matthew Powell

Jeffrey Lee Sonntag

Kenneth Wilson Fernald

Bertrand Jeffery Williams

Dazhi Wei

Jinwen Xiao

Timothy Thomas Rueger

Shouli Yan

Praveen Kallam

Dewitt Clinton Seward, Iv

Hatem M Osman

Imranul Islam

Erik Pankratz

In one aspect, an apparatus includes: a first feedback digital-to-analog converter (DAC) to receive a first feedback signal from a first successive approximation register (SAR) and output a first analog signal; a comparator to compare the first analog signal with a reference voltage; the first SAR to store a digital value based on the comparison and provide the first feedback signal to the first DAC; a second feedback DAC to receive a modulated quantized residual error based on the comparison and output a second analog signal; a second SAR to store a quantized residual error; and a delta-sigma modulator (DSM) to modulate the quantized residual error and provide the modulated quantized residual error to the second feedback DAC.

Noise-shaping converter with digital modulator

In one embodiment, an apparatus includes: a replica sampler circuit to sample a first voltage that is based on a reference voltage, the replica sampler circuit to at least approximate a non-linearity of a bias generator. The replica sampler circuit may include: a switch circuit, when enabled, to pass the first voltage; and a capacitor coupled to the switch circuit, the capacitor to be charged by the first voltage. The apparatus also may include a comparator coupled to the replica sampler circuit, the comparator having a first input terminal to receive the sampled first voltage and a second input terminal to receive the reference voltage, where the comparator is to output a first signal having a first value when the sampled first voltage departs from the reference voltage by at least a threshold amount, to cause a refresh of at least a portion of the bias generator.

Adaptive refresh rate generator

Positive and negative glitch detectors detect glitches on a supply voltage node. The positive glitch detector has a capacitor and a resistor serially coupled between the supply voltage node and ground. An amplifier is coupled to a first node between the capacitor and resistor. A positive glitch results in the glitch on the first node (normally biased low) and generation of a clock pulse by the amplifier that causes a latch to assert its output to indicate the positive glitch. The negative glitch detector has a capacitor and resistor coupled in parallel between the supply voltage node and a second node. A negative glitch on the supply voltage node decreases the voltage on the second node (normally biased high) and an inverting amplifier coupled to the second node generates a clock pulse to cause a latch to assert its output to indicate the negative voltage glitch.

Voltage glitch detectors

A physically unclonable function (PUF) includes a bit cell that includes a latch and a switch to selectively couple the latch to a supply voltage node. A first transmission gate couples a first bit line to a first internal node of the latch and a second transmission gate couples a second bit line to a second internal node of the latch. A digital to analog converter (DAC) circuit is selectively coupled to the first internal node through the first bit line and the first transmission gate and to the second internal node through the second bit line and the second transmission gate, to thereby precharge the latch before the first bit cell is read. The latch regenerates responsive to the switch being closed to connect the latch to the supply voltage node. The first and second bit lines are used to read the regenerated value of the latch.

Physically unclonable function with precharge through bit lines

In one embodiment, an apparatus includes a controller to control a voltage regulator. The controller may have a first comparator circuit to compare a first reference voltage to a feedback voltage. In turn, the first comparator circuit may include: a first comparator having a first input terminal to receive the feedback voltage and a second input terminal to receive the reference voltage and an output node to output an error signal based on the comparison; and a first pre-charge circuit coupled between the first input terminal and the output node configured to pre-charge a first portion of a compensation network to a pre-charge level. The first controller may further include a second comparator circuit coupled to the first comparator circuit compare the error signal to a ramp signal and to generate a first control output to control a power train of the voltage regulator in a first mode of operation.

Pre-charge technique for a voltage regulator

An apparatus includes a first field effect transistor (FET) that has a body and is coupled in a circuit. The apparatus also includes a second FET that has a body and is coupled in the circuit. The circuit has an offset because of a mismatch. The apparatus further includes an offset correction circuit coupled to the body of the first FET and to the body of the second FET. The offset correction circuit provides a first offset correction signal to the body of the first FET and provides a second offset correction signal to the body of the second FET.

Apparatus for offset correction in electronic circuitry and associated methods

An apparatus includes a multi-stage amplifier. The multi-stage amplifier includes first, second, and third amplifier circuits coupled in a cascade configuration. The multi-stage amplifier further includes first, second, and third compensation networks. The first compensation network is coupled between the output of the third amplifier circuit and the input of the second amplifier circuit. The second compensation network is coupled between the output of the third amplifier circuit and the input of the third amplifier circuit. The third compensation network is coupled between the output of the second amplifier circuit and the input of the second amplifier circuit.

Apparatus for compensation of electronic circuitry and associated methods

A method of operating an amplifier circuit having a pre-charge phase and a sample/conversion phase includes, during a pre-charge phase, charging first and second capacitors to first and second bias voltages. The first capacitor is coupled to a first input of an amplifier circuit, which has a second input and an output. The second capacitor is coupled to the second input. During a sample/conversion phase, the first input of the amplifier circuit is coupled to an input signal through the first capacitor to level-shift the input signal according to the first bias voltage and the output of the amplifier is coupled to the second input through the second capacitor to level shift a feedback signal according to the second bias voltage.

Growing community of inventors

Austin, TX, United States of America

Gang Yuan