Montage Electronics (Shanghai) Co., Ltd.

Integrated Device Technology, Inc.

Montage Technology (Shanghai) Co., Ltd.

Montage Technology Group Limited

Noark Electrics (Shanghai) Co. Ltd.

Noark Electrics Co. Ltd.

Gang Yan

Zhongyuan Chang

Pengzhan Zhang

Liang Zhang

Yong Wang

Jie Zhang

Larry Wu

Xiaomin Si

Xuexin Ding

Lixin Jiang

Pengbin Yan

YuFei Gu

Qiuyan Zu

Li Quan

Zongjie Hu

Wenjuan Zhang

Yu Zhong

The disclosure provides a multi-mode frequency division circuit including a frequency division factor processor, a frequency divider, and a logic operator. The frequency division factor processor receives the frequency division factor, decomposes the frequency division factor to obtain a first sub-frequency division factor and a second sub-frequency division factor, and outputs the first sub-frequency division factor or the second sub-frequency division factor according to a frequency division clock signal. The divider performs frequency division on the clock signal based on the first sub-frequency division factor or the second sub-frequency division factor to generate the frequency division clock signal. The logic operator sequentially samples the frequency division clock signal according to the rising edge and falling edge of the clock signal to generate a first signal and a second signal, and the logic operator generates an output clock signal according to the first signal, the second signal, and an indication signal.

Multi-mode frequency division circuit

A method for obtaining board parameters of a printed circuit board, including the following steps: obtaining parameter information of a stripline on the printed circuit board; obtaining physical parameters of the stripline based on the parameter information of the stripline and a predetermined electromagnetic simulation application; calculating required board parameters of the printed circuit board based on the parameter information and the physical parameters of the stripline. In the present disclosure, the physical parameters of the stripline are obtained based on the physical nature of the stripline on the printed circuit board, and there is no need for fitting or adopting a hypothetical model in order to obtain board parameters corresponding to each frequency point of the stripline; the present disclosure is simple and straightforward during operation, and the obtained board parameters of the printed circuit board are highly accurate.

Method for obtaining board parameters of printed circuit board

The disclosure provides a glitch removal circuit with low latency. The glitch removal circuit includes a first signal edge detector, a second signal edge detector, a latch, and a control signal generator. The first signal edge detector is activated according to the first control signal to detect the rising edge of the input signal to generate the first detection result. The second signal edge detector is activated according to the second control signal to detect the falling edge of the input signal to generate the second detection result. The latch sets the generated output signal according to the first detection result, and clears the generated output signal according to the second detection result. The control signal generator shields the glitch on the input signal to generate a processed signal, and generates a first control signal and a second control signal according to the processed signal.

Glitch removal circuit

A voltage regulator comprises a first amplifier and a biasing unit. The first amplifier has a positive input, a negative input and an output, wherein the output of the amplifier is connected to the negative input. The biasing unit generates a reference voltage by Complementary Metal-Oxide-Semiconductor transistors, wherein the positive input of the first amplifier is configured to receive the reference voltage.

Voltage regulator and method of regulating voltage

A handle locking device for a modularized terminal electric appliance is presented. A housing base thereof can be assembled onto any outer side surface of the housing of an appliance through a connection mechanism. There are a horizontal pivoting door and a vertical pivoting door which can be unfolded or folded inside a door hole on a sliding member of the locking mechanism. When unfolded, the horizontal pivoting door mates with an appliance handle to block the reverse motion of the handle, and the vertical pivoting door and the horizontal pivoting door can mate to block the reverse motion of the unfolded horizontal pivoting door. The horizontal pivoting door is pivotally connected to the sliding member through a horizontal pivoting, and the vertical pivoting door is pivotally connected to the sliding member through a vertical pivoting. A padlock is provided with a lock ring which can penetrate the interconnected door hole from a padlock hole and the lock ring can mate with the vertical pivoting door to block the reverse motion of the unfolded vertical pivoting door. The locking mechanism is connected and mounted with the housing base through a moving pair and can only perform up/down sliding along the direction of an assembly reference line B parallel to the appliance height direction Y, the locking mechanism is defined to slide merely between the locking and unlocking positions thereof, and adjustable height position of the locking device under the two states of handle locking and unlocking is realized by way of the shift of the sliding member.

Handle locking device for modularized terminal electric appliance

Methods and apparatuses to terminate transmission lines using voltage limiters. In one aspect, a termination circuit is integrated on a substrate to terminate a transmission line connected from outside the substrate. The termination circuit includes: a port to interface with the transmission line; a first resistive path including a first voltage limiter coupled between the port and a first power supply voltage provided on the substrate resistive path; and a second resistive path including a second voltage limiter coupled between the port and a second power supply voltage provided on the substrate.

On-die termination circuit

A phase-locked loop (PLL) includes a phase-frequency detector circuit configured to detect an error of an output clock signal in relation to a reference clock signal and to generate a charge pump control signal therefrom and a charge pump circuit configured to charge and discharge an output node thereof responsive to the charge pump control signal. The PLL further includes a current-mode loop filter circuit coupled to the output node of the charge pump circuit and configured to generate a filtered current from the current at the output node of the charge pump circuit, and a current-controlled oscillator configured to generate the output clock signal responsive to the filtered current. The current-mode loop filter circuit may be self-biased. For example, the current-mode loop filter circuit and the charge pump may be biased responsive to a common bias control signal generated by the current-mode loop filter circuit.

Phase-locked loop circuits with current mode loop filters

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Shanghai, China

Gang Yan