Intel Corporation

Synopsys, Inc.

Gang Y Chen

Subramaniam M Maiyuran

Guei-Yuan Lueh

Supratim Pal

Abhishek R Appu

Joydeep Ray

Altug Koker

Prasoonkumar Surti

Travis T Schluessler

Ankur N Shah

David M Puffer

Devan Burke

Jonathan Kennedy

Jorge E Parra

Wei-Yu Chen

Chandra S Gurram

Ashutosh Garg

Darin Starkey

Joy Chandra

Hong Bin Liao

Ananda V Kommaraju

Bret L Toll

Varghese George

Rajesh M Sankaran

William Rash

Jianfeng Luo

Examples described herein relate to a software and hardware optimization that manages scenarios where a write operation to a register is less than an entirety of the register. A compiler detects instructions that make partial writes to the same register, groups such instructions, and provides hints to hardware of the partial write. The execution unit combines the output data for grouped instructions and updates the destination register as single write instead of multiple separate partial writes.

Compiler assisted register file write reduction

Graphics processing systems and methods are described. A graphics processing apparatus may comprise one or more graphics processing engines, a memory, a memory management unit (MMU) including a GPU second level page table and GPU dirty bit tracking, and a provisioning agent to receive a request from a virtual machine monitor (VMM) to provision a subcluster of graphics processing apparatuses, the subcluster including a plurality of graphics processing engines from a plurality of graphics processing apparatuses connected using a scale-up fabric, provision the scale-up fabric to route data within the subcluster of graphics processing apparatuses, and provision a plurality of resources on the graphics processing apparatus for the subcluster based on the request from the VMM.

Virtualization and multi-tenancy support in graphics processors

An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

Control flow mechanism for execution of graphics processor instructions using active channel packing

Graph analysis for double pattern lithography is described. Layout shapes are decomposed into rectangles and a vertex is provided for each rectangle. Double pattern spacing conflicts are determined and shown as edges for the graph analysis. Odd cycles are used to identify double pattern lithography violations. Cycles can be completed with the addition of edges between vertices where stitches have been included in the layout. Edges between touching shapes do not count toward the odd count in the cycles. Fixes are included by increasing space or by rerouting. A portion of the layout can be incrementally changed and a local update of the graph analysis performed. Correct by construction layout is implemented by avoiding certain odd cycle prone layout routings.

Routing analysis with double pattern lithography

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Milpitas, CA, United States of America

Gang Y Chen