Yangtze Memory Technologies Co., Ltd.

Wuhan Taipu Transformer Changer Co., Ltd.

Tobacco Research Institute of Hubei Province

Gang Liu

Jin Lyu

Kaijin Huang

Zhi-Jiang Xu

Zhi-Biao Ding

Chunlei Yang

Jinpeng Yang

Kai Jin Huang

Jun Yu

Kaixiao Fan

Xin Wang

Youlun Fan

Sicheng Liu

Jiazhen Chen

Chuanzong Li

Liguang Chai

Yong Rao

Yu Song

Yiyang Zhang

Zhenxin Wu

Zhilong Bie

Yuan Huang

Wenchang Huang

Yulei Zhao

Zhibiao Ding

Zhijiang Xu

The present disclosure provides a supplemental lighting method for vertical multi-layer cultivation of wrapper tobacco leaves, including the following steps: providing multi-layer vertical facilities, facilities including at least one cultivation rack having a plurality of layers; and providing supplemental lighting systems to each rack layer. For each rack layer the light intensity and light quality provided by the corresponding supplemental lighting system are set respectively according to a determined growth phase of the tobacco leaves during the cultivation process. The process includes cultivation of tobacco leaves through growth phases comprising a clumping period, a vigorous growth period, and a maturity period. During the clumping period, the light intensity provided comprises a first light intensity setting. During the vigorous growth period, the light intensity provided comprises a third light intensity setting. During the maturity period, the light intensity provided comprises a second light intensity setting.

Supplemental lighting method for vertical multi-layer cultivation of wrapper tobacco leaves

A memory device, a system, and a method for operating the memory device are provided. The memory device includes a first memory string and a peripheral circuit. The first memory string includes a first drain, a first drain select gate (DSG) transistor, a first drain dummy transistor between the first drain and the first DSG transistor, and a plurality of first memory cells. A first drain dummy line is coupled to the first drain dummy transistor, and a first DSG line is coupled to the first DSG transistor. The peripheral circuit is configured to, in a program operation, apply a first DSG voltage to the first DSG line and apply a first drain dummy line voltage to the first drain dummy line to turn on the first drain dummy transistor. The first drain dummy line voltage is greater than the first DSG voltage.

Memory device and program operation thereof

In certain aspects, a memory device includes a first memory string including a first drain, a first drain select gate (DSG) transistor, first memory cells, and a first drain dummy transistor between the first drain and the first DSG transistor. The memory device also includes a first bit line coupled to the first drain, a first drain dummy line coupled to the first drain dummy transistor, a first DSG line coupled to the first DSG transistor, word lines respectively coupled to the first memory cells, and a peripheral circuit configured to perform a program operation on a target memory cell of the first memory cells coupled to a selected word line of the word lines. To perform the program operation, the peripheral circuit includes a bit line driver coupled to the first bit line and configured to apply a first bit line voltage to select the first bit line, and a word line driver coupled to the first drain dummy line and the first DSG line and configured to apply a DSG voltage to the first DSG line to turn on the first DSG transistor, and apply a drain dummy line voltage to the first drain dummy line to turn on the first drain dummy transistor. The drain dummy line voltage is greater than the DSG voltage.

An operation method for a 3D NAND flash having a plurality of bit lines, wherein the plurality of bit lines comprises a plurality of layers, the operation method includes defining a plurality of upper layers of the plurality of bit lines of the 3D NAND flash as a plurality of upper select gates and a top layer of the plurality of bit lines of the 3D NAND flash as a top dummy layer; and applying a first voltage on a first top dummy layer of a select bit line of the plurality of bit lines to turn on the first top dummy layer of the select bit line of the plurality of bit lines when programming.

Operation method for 3D NAND flash and 3D NAND flash

One aspect of the present invention, a strip type off-circuit tap changer includes an insulating rod and a support, where an operation positioning device is arranged on the support, a rack mobile frame is disposed on the insulating rod, the rack of the rack mobile frame is engaged to a drive gear of the operation positioning device, columnar fixed contacts are longitudinally arranged at a spacing on the insulating rod, the rack mobile frame is connected to a moving contact frame, and a moving contact assembly is arranged on the moving contact frame and fits with the fixed contacts on the insulating rod, the moving contact assembly is formed by an annular moving contact and an elastic pin, and the annular moving contact spans between two adjacent columnar fixed contacts.

Strip type off-circuit tap changer

In one aspect of the invention, an off-circuit tap changer includes a switch base and a rotation shaft penetrating the switch base. An upper end of the rotation shaft is connected to an operation positioning device, a lower end of the rotation shaft is disposed with moving contacts, and fixed contacts corresponding to the moving contacts are circumferentially disposed at a spacing on the switch base; the moving contacts are radial elastic rolling moving contacts, and the radial elastic rolling moving contacts span between two adjacent fixed contacts and closely contact the fixed contacts.

Off-circuit tap changer

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Wuhan, China

Gang Liu