Chip Memory Technology, Inc.

Gang-Feng Fang

Wingyu Leung

A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least one non-volatile memory cell consists of a SONOS transistor fabricated on a P substrate, with a deep N-well located in the P substrate, with a P-well located in the deep N-well. The memory cell further includes an access NMOS transistor, coupled to the SONOS transistor and located in the same P-well that includes an oxide only gate-dielectric. The cell can be fabricated in a modified logic process with other transistors and with their physical characteristics preserved.

N-channel SONOS non-volatile memory for embedded in logic

An apparatus and method of an electrically programmable and erasable non-volatile memory cell with a deep N-well to isolate the memory cell from the substrate is disclosed. In one embodiment, a non-volatile memory apparatus includes at least one non-volatile memory cell fabricated on a P substrate, with a deep N-well located in the P substrate, while a P-well and an N-well are located in the deep N-well. The memory cell further includes a PMOS transistor located in the N-well, in which the PMOS transistor includes a PMOS gate-oxide, and an NMOS capacitor located in the P-well. The NMOS capacitor includes an N+ coupling region located in the P-well, and an NMOS gate-oxide. The memory cell further includes a floating gate comprised of a poly-silicon gate overlying the PMOS transistor and the NMOS capacitor.

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Fremont, CA, United States of America

Gang-Feng Fang