Mosys, Inc.

Gang-feng Fang

Wingyu Leung

Dennis Sinitsky

A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.

Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process

A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).

Non-volatile memory in CMOS logic process

A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.

Non-volatile memory embedded in a conventional logic process and methods for operating same

A non-volatile memory (NVM) cell fabricated on a semiconductor substrate, and including a floating gate electrode (which extends at least partially over all active regions of the NVM cell). The NVM cell also includes a PMOS access transistor located in a first n-type region, a PMOS control capacitor located in a second n-type region (separate from the first n-type region), and an NMOS programming transistor located in a p-type region. The floating gate electrode is a continuous electrode which extends over the active regions of the PMOS access transistor, the PMOS control capacitor and the NMOS programming transistor. Various array connections are provided for implementing arrays using this NVM cell. The PMOS access transistor and NMOS programming transistor can be replaced with an NMOS access transistor and a PMOS erase transistor, respectively, in an alternate embodiment.

Growing community of inventors

Alameda, CA, United States of America

Gang-feng Fang