Meta Platforms Technologies, LLC

Intel Corporation

Meta Platforms, Inc.

Nvidia Corporation

Facebook Technologies, LLC

Ganesh Venkatesh

Deborah T Marr

Pierce I-Jen Chuang

Liangzhen Lai

Nicholas P Carter

Robert Valentine

Gilbert A Neiger

Mark Jay Charney

Jesus Corbal

Rajesh M Sankaran

Edward Thomas Grochowski

Eriko Nurvitadhi

Koichi Yamada

Thomas D Fletcher

Joseph Nuzman

Stephen R Van Doren

Paul Caprioli

Lokpraveen B Mosur

Dennis Ryan Bradford

Narayan Ranganathan

Kent D Glossop

Niall D McDonnell

Jonathan D Pearce

Richard J Greco

Jeffrey J Cook

Asit K Mishra

Dwight P Manley

David B Sheffield

Tracy Garrett Drysdale

Michael A O'Hanlon

Meng Li

Vikas Chandra

Jack H Choquette

Brian Keith Cabral

Ming Yiu Siu

Ronny Krashinsky

Manan Patel

Samuel Alan Johnson

Jorge Albericio Latorre

Albert Parra Pozo

Michael Alexander Snower

Amit Kumar

Rakesh Ranjan

Yash Patel

Alagappan Valliappan

Joseph Virskus

Kai Li

Shen-Chi Chen

Wei Ye

Christopher B Wilkerson

Harshit Khaitan

Chengyuan Yan

Seth H Pugsley

Jeffrey Michael Pool

John Tran

Feng Xie

Jeff Pool

John Jacob Blakeley

Amy Lawson Bearman

Suchit Subhaschandra

Simon James Hollis

Christopher E Balmes

Alireza Dirafzoon

Matthew Dan Feiszli

Yiming Pu

Srivatsan Krishnan

Gabrielle Catherine Moskey

Babak Damavandi

Guangqiang Dong

Jiwen Ren

Niall D Mcdonnell

Michael A O'HANLON

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

A holographic calling system can capture and encode holographic data at a sender-side of a holographic calling pipeline and decode and present the holographic data as a 3D representation of a sender at a receiver-side of the holographic calling pipeline. The holographic calling pipeline can include stages to capture audio, color images, and depth images; densify the depth images to have a depth value for each pixel while generating parts masks and a body model; use the masks to segment the images into parts needed for hologram generation; convert depth images into a 3D mesh; paint the 3D mesh with color data; perform torso disocclusion; perform face reconstruction; and perform audio synchronization. In various implementations, different of these stages can be performed sender-side or receiver side. The holographic calling pipeline also includes sender-side compression, transmission over a communication channel, and receiver-side decompression and hologram output.

Holographic calling for artificial reality

In one embodiment, a method includes rendering a first output image comprising one or more augmented-reality (AR) objects for displays of an AR rendering device of an AR system associated with a first user. The method further includes accessing sensor signals associated with the first user. The one or more sensor signals may be captured by sensors of the AR system. The method further includes detecting a change in a context of the first user with respect to a real-world environment based on the sensor signals. The method further includes rendering a second output image comprising the AR objects for the displays of the AR rendering device. One or more of the AR objects may be adapted based on the detected change in the context of the first user.

Dynamic content rendering based on context for AR and assistant systems

In one embodiment, a method for machine learning acceleration includes receiving, by a shared controller of a tensor processor cluster that includes multiple tensor processors, a multi-cycle instruction, determining, based on the instruction, a sequence of vector operations to be executed by the tensor processors and address information usable to determine a respective spatial partition of an input tensor on which each tensor processor is to operate when performing each vector operation. The method also includes, for each vector operation in the sequence, generating, based on the address information, a common address offset, relative to a respective base address associated with each tensor processor, at which each tensor processor is to retrieve the respective spatial partition on which the tensor processor is to operate, multicasting the common address offset to the tensor processors, and controlling the tensor processors to execute the vector operation in parallel and in lock step.

Spatial tiling of compute arrays with shared control

Disclosed herein includes a system, a method, and a device for reading and writing sparse data in a neural network accelerator. A mask identifying byte positions within a data word having non-zero values in memory can be accessed. Each bit of the mask can have a first value or a second value, the first value indicating that a byte of the data word corresponds to a non-zero byte value, the second value indicating that the byte of the data word corresponds to a zero byte value. The data word can be modified to have non-zero byte values stored at an end of a first side of the data word in the memory, and any zero byte values stored in a remainder of the data word. The modified data word can be written to the memory via at least a first slice of a plurality of slices that is configured to access the first side of the data word in the memory.

Systems and methods for reading and writing sparse data in a neural network accelerator

A machine-learning accelerator system, comprising: a plurality of controllers each configured to traverse a feature map with n-dimensions according to instructions that specify, for each of the n-dimensions, a respective traversal size, wherein each controller comprises: a counter stack comprising counters each associated with a respective dimension of the n-dimensions of the feature map, wherein each counter is configured to increment a respective count from a respective initial value to the respective traversal size associated with the respective dimension associated with that counter; a plurality of address generators each configured to use the respective counts of the counters to generate at least one memory address at which a portion of the feature map is stored; and a dependency controller computing module configured to (1) track conditional statuses for incrementing the counters and (2) allow or disallow each of the counters to increment based on the conditional statuses.

Tensor controller architecture

Disclosed herein includes a system, a method, and a device for processing and converting data using matrix operations. Circuitry can partition an input of a first data format across a plurality of lookup tables each residing in a respective memory. The circuitry can access weight information from a load store memory, and the partitioned input on a per column basis from the plurality of lookup tables. The circuitry can perform a number of multiply-accumulate (MAC) operations per cycle between the weight information from the load store memory and the partitioned input read on a per column basis from the plurality of lookup tables. The number of MAC operations performed per cycle can correspond to a total number of columns of the plurality of lookup tables. The circuitry can generate, responsive to the MAC operations on the partitioned input, a plurality of outputs in a second data format.

Systems and methods for speech or text processing using matrix operations

Disclosed herein is a method for using a neural network across multiple devices. The method can include receiving, by a first device configured with a first one or more layers of a neural network, input data for processing via the neural network implemented across the first device and a second device. The method can include outputting, by the first one or more layers of the neural network implemented on the first device, a data set that is reduced in size relative to the input data while identifying one or more features of the input data for processing by a second one or more layers of the neural network. The method can include communicating, by the first device, the data set to the second device for processing via the second one or more layers of the neural network implemented on the second device.

Systems and methods for distributing a neural network across multiple computing devices

Disclosed herein includes a system, a method, and a device for improving computational efficiency of deconvolution by reducing a number of dot products. In one aspect, an input image having a set of pixels is received. A first dot product may be performed on a subset of the set of pixels of the input image and a portion of a kernel, to generate a first pixel of an output image. A number of multiplications performed for the first dot product performed may be less than a number of elements of the kernel. A second dot product on a remaining portion of the kernel to generate the first pixel of the output image may be bypassed.

Optimization for deconvolution

Disclosed herein includes a system, a method, and a device for receiving input data to generate a plurality of outputs for a layer of a neural network. The plurality of outputs are arranged in a first array. Dimensions of the first array may be compared with dimensions of a processing unit (PE) array including a plurality of PEs. According to a result of the comparing, the first array is partitioned into subarrays by the processor. Each of the subarrays has dimensions less than or equal to the dimensions of the PE array. A first group of PEs in the PE array is assigned to a first one of the subarrays. A corresponding output of the plurality of outputs is generated using a portion of the input data by each PE of the first group of PEs assigned to the first one of the subarrays.

System and method for performing small channel count convolutions in energy-efficient input operand stationary accelerator

Disclosed herein includes a system, a method, and a device for reading and writing sparse data in a neural network accelerator. A plurality of slices can be established to access a memory having an access size of a data word. A first slice can be configured to access a first side of the data word in memory. Circuitry can access a mask identifying byte positions within the data word having non-zero values. The circuitry can modify the data word to have non-zero byte values stored starting at an end of the first side, and any zero byte values stored in a remainder of the data word. A determination can be made whether a number of non-zero byte values is less than or equal to a first access size of the first slice. The circuitry can write the modified data word to the memory via at least the first slice.

Disclosed herein includes a system, a method, and a device for performing a convolution on data of a current layer of a neural network, including a plurality of channels arranged in a first order and partitioned into a plurality of first partitions according to the first order. Each first partition includes a result of a convolution on a corresponding partition of channels in data of a previous layer of the neural network. The device shifts the plurality of channels arranged in the first order to a second order, partition the shifted plurality of channels into a plurality of second partitions, according to the second order. For each of the plurality of second partitions, the device performs a convolution on channels of the shifted plurality of channels that are in the corresponding second partition.

System and method for shift-based information mixing across channels for shufflenet-like neural networks

Disclosed herein includes improving computational efficiency of multiply-accumulate (MAC) operation. In one aspect, a computing device identifies, a first vector including non-zero elements of a base matrix, and a second vector indicating a location of each of the non-zero elements of the base matrix. In one aspect, the device determines a first element and a second element of the first vector. In one aspect, the device determines a third element and a fourth element of the second vector. In one aspect, the device determines i) a fifth element of an input vector according to the third element of the second vector, and ii) a sixth element of the input vector according to the fourth element of the second vector. In one aspect, the device causes a MAC circuitry to perform a dot product according to the first element, the second element, the fifth element, and the sixth element.

Efficient multiply-accumulation based on sparse matrix

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San Jose, CA, United States of America

Ganesh Venkatesh