Lam Research Corporation

Globalfoundries Inc.

Lam Research Corportation

Ganesh Upadhyaya

Yoshie Kimura

Xiang Zhou

Chen Xu

Duming Zhang

Mitchell Brooks

Qinghua Zhong

Gowri Kamarthy

Radhika C Mani

Naveed Ansari

Kazi Sultana

Haseeb Kazi

Si-Yi Yi Li

Qian Fu

Taejoon Han

Yoko Yamaguchi

Hoong Shing Wong

Gabriel Padron Wells

Chang Ho Maeng

Xing Zhang

Noel Sun

Helene Del Puppo

Tae Won Kim

Gladys Lo

Ming-Shu Kuo

Kristina Trevino

Ryan Martin

Weiye Zhu

Yuan-Hung Liu

Zhaohong Han

Isabelle Orain

Seokhwan Lee

Methods and apparatuses for critical dimension (CD) control of substrate features using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include etching to form a mask pattern of features on a substrate having a width that is less than a desired width of structures to be subsequently formed by the mask pattern of features, conformally depositing a passivation layer by ALD that increases the width of the mask pattern of features to the desired width, and etching a layer of the substrate to a desired depth to form the plurality of structures having the desired width.

Atomic layer deposition and etch in a single plasma chamber for critical dimension control

Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.

Atomic layer deposition and etch for reducing roughness

Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.

Atomic layer deposition and etch in a single plasma chamber for fin field effect transistor formation

Methods, systems, and computer programs are presented for optimizing Critical Dimension Uniformity (CDU) during the processing of a substrate. One method includes identifying an operation of a recipe for processing a substrate within a chamber, the operation being configured to provide a pulsed radio frequency (RF) to the chamber. A plurality of tests are performed in the chamber for the operation utilizing the pulsed RF, each test having a duty cycle for the pulsed RF selected from a plurality of RF duty cycles. The method also includes for each test, measuring the critical dimension (CD) and the CDU for features in the substrate, and selecting a first duty cycle from the plurality of RF duty cycles based on the measured CDs and CDUs for the plurality of tests. The method also includes setting the selected first duty cycle in the operation of the recipe for processing the substrate.

Determination of semiconductor chamber operating parameters for the optimization of critical dimension uniformity

Systems and methods for etching a substrate include arranging a substrate including a first structure and a dummy structure in a processing chamber. The first structure is made of a material selected from a group consisting of silicon dioxide and silicon nitride. The dummy structure is made of silicon. Carrier gas is supplied to the processing chamber. Nitrogen trifluoride and molecular hydrogen gas are supplied to the processing chamber. Plasma is generated in the processing chamber. The dummy structure is etched.

Residue free systems and methods for isotropically etching silicon in tight spaces

Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

Semiconductor structures with coplanar recessed gate layers and fabrication methods

A method for forming devices with silicon gates over a substrate is provided. Silicon nitride spacers are formed on sides of the silicon gates. An ion implant is provided using the silicon nitride spacers as masks to form ion implant regions. A nonconformal layer is selectively deposited over the spacers and gates that selectively deposits a thicker layer on tops of the gates and spacers and between spacers than on sidewalls of the silicon nitride spacers. Sidewalls of the nonconformal layer are etched away on sidewalls of the silicon nitride spacers. The silicon nitride spacers are trimmed.

Silicon nitride dry trim without top pulldown

Growing community of inventors

Pleasanton, CA, United States of America

Ganesh Upadhyaya