Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

National University of Singapore

Other

Ganesh S Samudra

King Jien Chui

Kheng Chok Tee

Alex See

Yisuo Li

Francis Benistant

Yee Chia Yeo

Kian Meng Tee

Kum Woh Vincent Leong

Sneedharan Pillai Sneelal

C K Lau

Lap Chan

Mei Sheng Zhou

Jinping Liu

Yung Fu Chong

Kin Leong Pey

James Yong Meng Lee

Yihong Wu

Francis YongWee Poh

James Yongmeng Lee

Kuang Kian Ong

Andrew Khoh

Yung Chii Liang

Lydia Wong

Byong-Il Choi

Wee Hong Phua

Kian Paau Gan

Xin Yang

Francis Youg Wee Poh

Krishnasamy Rajendran

Chi Kwan Lau

A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.

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A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

Structure and method to form source and drain regions over doped depletion regions

A trial semiconductor photomask design having discontinuity points is provided, and each of the discontinuity points is treated as simulated light sources. Simulated light from each of the simulated light sources is focused, and a composite image intensity of the focused simulated light is calculated to verify the trial semiconductor photomask design. The trial semiconductor photomask design is sharpened. A photomask design specification is generated for use in fabricating such a photomask.

System and method for designing semiconductor photomasks

A method of manufacturing a semiconductor device provides a semiconductor substrate with a gate and a number of source/drain regions on the semiconductor substrate. A layer containing a strain-inducing element is provided over the number of source/drain regions. The strain-inducing element is driven from the layer containing a strain-inducing element into the number of source/drain regions. A number of source/drains is formed in the number of source/drain regions.

Method of manufacturing a semiconductor device with a strained channel

A method for forming a self-aligned, recessed channel, MOSFET device that alleviates problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A thin pad oxide layer is grown overlying the substrate and a gate recess, followed by deposition of a thick silicon nitride layer filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown, thickening the pad oxide layer. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown. This forms a tapered oxide layer along the sidewalls of the gate recess. The remaining silicon nitride layer is removed. The oxide layer at the bottom of the gate recess is removed and a gate dielectric layer is grown. Gate polysilicon is deposited filling the gate recess. S/D implantations, metallization, and passivation complete fabrication of the device.

Process flow for a performance enhanced MOSFET with self-aligned, recessed channel

A MOSFET includes a dielectric, preferably in the form of a metal thick oxide that extends alongside the MOSFET's drift region. A voltage across this dielectric between its opposing sides exerts an electric field into the drift region to modulate the drift region electric field distribution so as to increase the breakdown voltage of a reverse biased semiconductor junction between the drift region and body region. This allows for higher doping of the drift region, for a given breakdown voltage when compared to conventional MOSFETs.

Power MOSFET having enhanced breakdown voltage

A method for forming a self-aligned, recessed channel, MOSFET device that alleviates the problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A substrate with an active area encompassed by a shallow trench isolation (STI) region is provided. A mask oxide layer is then patterned and etched to expose the substrate and a portion of the STI region. The surface is etched and the mask oxide layer is eroded away while creating a gate recess in the unmasked area. A thin pad oxide layer is then grown overlying the surface followed by a deposition of a thick silicon nitride layer covering the surface and filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown causing the pad oxide layer to thicken. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown causing the pad oxide layer to further thicken. This forms a tapered oxide layer along the sidewalls of the gate recess. The remaining silicon nitride layer is then removed, re-opening the gate recess. A threshold adjust and punch-through implantation is performed into the substrate below the gate recess. The pad oxide layer is then isotropically etched to remove the oxide layer at the bottom of the gate recess and a gate dielectric layer is grown in the bottom of the gate recess. Gate polysilicon is then deposited covering the top surface and filling the gate recess. The top surface is again planarized to expose the substrate. A screen oxide layer is then deposited, followed by light and heavy S/D implantations and annealing. Metalization and passivation complete the fabrication of the MOS transistor device.

A process for forming a groove in a semiconductor substrate, to be used to fabricate grooved gate, MOSFET devices, has been developed. The process features the use of an insulator mask, used as an etch mask for definition of the groove feature in the semiconductor substrate. A selective, anisotropic RIE procedure, using an etchant with a specific etch rate ratio of silicon, (semiconductor substrate), to silicon oxide, (insulator mask), is used to establish the desired groove depth, in the semiconductor substrate. The combination of a specific thickness of insulator shape, and a specific etch rate ratio for the selective, anisotropic RIE procedure, allows the desired depth of the groove to be established when the insulator shape is completely removed from the top surface of the semiconductor substrate. The groove depth established at this point of the RIE procedure, will not change during an overetch cycle, as a result of etching the now exposed, top surface of the semiconductor surface, at the same rate as exposed semiconductor, located at the bottom of the groove.

Process to achieve uniform groove depth in a silicon substrate

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Singapore, Singapore

Ganesh S Samudra