Nec Corporation

Alphion Corporation

Other

University of California

Lucent Technologies Inc.

Nec Electronics Corporation

Nec Usa, Inc.

Ganesh Lakshminarayana

Anand Raghunathan

Niraj K Jha

Boris Stefanov

Jithamithra Sarathy

Bharat P Dave

Jayanta Das

Sujit Dey

Kanishka Lahiri

Srimat T Chakradhar

Wolfgang Roethig

Ronald Simprini

Roman Antosik

Arun Balakrishnan

Hongsheng Wang

Ruomei Mu

Nachiketh Potlapally

Kamal S Khouri

Kuo-Ming Lee

Scott Kaminski

Michael S Hsiao

A method and apparatus to achieve a resource optimized, class of Reed Solomon decoders, featuring balanced pipelined stages and parallel algorithmic components. The Reed Solomon decoder has two pipeline stages, with one stage implementing syndrome computation and the second stage implementing error locator polynomial evaluation, error location and error correction. Since the second pipeline stage performs several tasks, these tasks can share resources with each other, resulting in a compact implementation. In addition, we present a technique that can be used to compute the level of parallelism required of two key algorithmic components (syndrome computation, error location) so that the RS decoder can handle inputs of variable rates, with minimal latency and resource consumption. We show that low latency, in itself, is an important consideration for Reed Solomon decoders, and can lead to reduced buffering, resulting in significant hardware savings.

Reed Solomon decoding of signals having variable input data rates

Monitoring of the input power is performed on-chip and is used to monitor and maintain performance, detect failure and trigger network protection strategies. An optical power-monitoring technique uses a photodetector monolithically integrated with the semiconductor optical amplifier&#x2014;Mach-Zehnder interferometer circuit to monitor the P2R device and keep the output stable while the input power varies.

Integrated performance monitoring, performance maintenance, and failure detection for photonic regenerators

A integrated optical circuit comprises an interferometer having a first optical path and a second optical path configured for regenerating an input signal entering the first path by interference at a first coupler between continuous wave (CW) signals from the two optical paths, and a third optical path configured such that a canceling signal passing therethrough cancels, at a second coupler, a traveling signal from the first arm. When the device is operated in a counter-propagative mode, the traveling signal is the CW signal from the first arm. When the device is operated in a co-propagative mode, the traveling signal is the input signal from the first arm.

Photonic integrated circuit

Method and apparatus are presented for the generation and detection of maintenance signals in an optical data network. The maintenance signals are such that they can be read both by high bit-rate and low bit-rate receivers. Detection of the maintenance signals occurs in two stages. In a low bit-rate first stage each nodal input port is sampled in a round robin fashion to detect the presence of a maintenance signal. In a high bit-rate second stage the maintenance signal is verified and read by a high speed receiver, along with other high bit-rate information transmitted with it. One second stage high speed receiver is shared among M input channels for cost and circuit efficiency.

Generation and detection of optical maintenance signals in optical networks

A method of designing a communication architecture comprising receiving a partitioned system, communication architecture topology, input traces and performance matrices. Analyzing and creating communication analysis graph (CAG). Partitioning communication instances to create partition clusters. Evaluating cluster statistics related to the partition clusters and assigning parameter values to the partition clusters to form a new system with new communication architecture. Reanalyzing the new system and recomputing performance metrics. If performance is improved then synthesizing CATs to realize optimized protocols. If performance is not improved then the process is repeated.

Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners

A method of creating models for power estimation of a circuit comprising generating an input space for the circuit. The input space is separated into multiple power modes corresponding to regions that display similar power behavior. Separate power models are generated for each of said multiple power modes. A power mode identification function is created that selects an appropriate power model from the separate power models based on the present and past values of the circuit inputs.

Power mode based macro-models for power estimation of electronic circuits

An electronic system with a plurality of components interconnected by a plurality of shared communication channels. At least one component comprises a communication architecture tuner. The tuner enables the electronic system to adapt to changing communication needs of the electronic system.

System for the design of high-performance communication architecture for system-on-chips using communication architecture tuners

The invention utilizes the linear complexity of orthogonal vectors to reduce the number of equations (or variables) to be solved. The present invention constructs a power model of a set of combinations of states without considering irrelevant combinations. The invention distinguishes between the switching direction on the input and the output pin. The invention considers state-dependency as a function of power consumed and depending on the paths through internal nodes. The model considers switching input pins that do not cause the output pin to switch to overcome inaccuracies caused by combining the power pin model with the state and arc power model with state. The model considers switching input pins that cause the output pin to switch. For cells in which the slewrate propagation effect from input to output is negligible, the invention uses a model of 2 power pins with state. The invention also determines the validity of this model. The present invention also models a power arc from one input pin to multiple output pins.

Multi-level power macromodeling

A method for designing a circuit with reduced power consumption using a Common-Case Computation (CCC) based design. The method comprising identifying a set of common case computations from a schedule of the circuit, designing add on common detection circuit that detects the set of common case computations, designing add on common case execution circuit that executes the set of common case computations; and integrating the add on circuitry with the original circuit. A circuit design system for optimizing a circuit for power management comprising: a simulator for simulating a schedule with input traces based on a given RTL design, schedule and typical input traces; a state sequence identifier for identifying promising state sequence patterns from simulated schedules; a behavior extractor for extracting behavior corresponding to each identified state sequences; a pattern selector for choosing a best pattern; a synthesizer for synthesizing common case circuitry; and an output generator for integrating common case circuitry with an original circuit.

Method for synthesis of common-case optimized circuits to improve performance and power dissipation

This present invention presents a Common Case Computation (CCC) based design. A computation circuit with reduced power consumption, said computation circuit having a plurality of components. The components include a general purpose circuit, a common case detection circuit and a common case execution circuit. The common case detection circuit detects an occurrence of a common case based on a first subset of primary inputs and a first subset of internal variables for the general purpose circuit, and the common case execution circuit computes a subset of primary outputs of the general purpose circuit based on a second subset of primary inputs for the general purpose circuits and a second subset of internal variables for the general purpose circuit. The first subset of the primary inputs and the first subset of internal variables can be the same as the second subset of primary variables and the second subset of internal variables respectively. The common case computation circuit identifies and exploits common case computations during the design process for reducing power consumption.

Common case optimized circuit structure for high-performance and low-power VLSI designs

A power management method and system targeted toward high-level synthesis of data-dominated behavioral descriptions. The method of the present invention is founded on the observation that variable assignment can significantly affect power management opportunities in the synthesized architecture. Based on this observation, a procedure for constraining variable assignment is provided so that the functional units in the synthesized architecture do not execute any spurious operations.

Constrained register sharing technique for low power VLSI design

Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network, etc.), 2) it supports both concurrent and sequential modes of communication and computation, 3) it employs a combination of preemptive and non-preemptive scheduling, 4) it introduces the concept of an association array to tackle the problem of multi-rate systems (which are commonly found in multimedia applications), 5) it uses a static scheduler based on deadline-based priority levels for accurate performance estimation of a co-synthesis solution, 6) it uses a new task clustering technique which takes the changing nature of the critical path in the task graph into account, 7) it supports pipelining of task graphs to derive a cost-efficient architecture, 8) it supports a mix of various technologies, such as 5 V CMOS, 3.3 V CMOS, 2.7 V CMOS, ECL, etc., to meet embedded system constraints and minimize power dissipation, and 9) if desired, it also optimizes the architecture for power consumption.

Growing community of inventors

Plainsboro, NJ, United States of America

Ganesh Lakshminarayana